any_div_1.tan.summary

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.982 ns
From           : clkout_3~reg0
To             : clkout_3
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 242.78 MHz ( period = 4.119 ns )
From           : cnt1[2]
To             : cnt1[31]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : clkout_3~reg0
To             : clkout_3~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 1

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1

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