📄 div12.tan.rpt
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Timing Analyzer report for div12
Mon Mar 26 16:41:45 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
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and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 6.876 ns ; clk_temp ; div12 ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[1] ; clk_temp ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+----------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[1] ; clk_temp ; clk ; clk ; None ; None ; 1.241 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[1] ; cnt[2] ; clk ; clk ; None ; None ; 1.239 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[2] ; clk_temp ; clk ; clk ; None ; None ; 1.172 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[2] ; cnt[1] ; clk ; clk ; None ; None ; 1.172 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[0] ; clk_temp ; clk ; clk ; None ; None ; 0.768 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[0] ; cnt[2] ; clk ; clk ; None ; None ; 0.766 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[0] ; cnt[1] ; clk ; clk ; None ; None ; 0.765 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; clk_temp ; clk_temp ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[1] ; cnt[1] ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[2] ; cnt[2] ; clk ; clk ; None ; None ; 0.501 ns ;
; N/A ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt[0] ; cnt[0] ; clk ; clk ; None ; None ; 0.501 ns ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+----------+-------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+----------+-------+------------+
; N/A ; None ; 6.876 ns ; clk_temp ; div12 ; clk ;
+-------+--------------+------------+----------+-------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Mon Mar 26 16:41:45 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div12 -c div12 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "cnt[1]" and destination register "clk_temp"
Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.241 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y5_N11; Fanout = 3; REG Node = 'cnt[1]'
Info: 2: + IC(0.482 ns) + CELL(0.651 ns) = 1.133 ns; Loc. = LCCOMB_X33_Y5_N18; Fanout = 1; COMB Node = 'clk_temp~23'
Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.241 ns; Loc. = LCFF_X33_Y5_N19; Fanout = 2; REG Node = 'clk_temp'
Info: Total cell delay = 0.759 ns ( 61.16 % )
Info: Total interconnect delay = 0.482 ns ( 38.84 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.817 ns
Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X33_Y5_N19; Fanout = 2; REG Node = 'clk_temp'
Info: Total cell delay = 1.756 ns ( 62.34 % )
Info: Total interconnect delay = 1.061 ns ( 37.66 % )
Info: - Longest clock path from clock "clk" to source register is 2.817 ns
Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X33_Y5_N11; Fanout = 3; REG Node = 'cnt[1]'
Info: Total cell delay = 1.756 ns ( 62.34 % )
Info: Total interconnect delay = 1.061 ns ( 37.66 % )
Info: + Micro clock to output delay of source is 0.304 ns
Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "div12" through register "clk_temp" is 6.876 ns
Info: + Longest clock path from clock "clk" to source register is 2.817 ns
Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
Info: 3: + IC(0.922 ns) + CELL(0.666 ns) = 2.817 ns; Loc. = LCFF_X33_Y5_N19; Fanout = 2; REG Node = 'clk_temp'
Info: Total cell delay = 1.756 ns ( 62.34 % )
Info: Total interconnect delay = 1.061 ns ( 37.66 % )
Info: + Micro clock to output delay of source is 0.304 ns
Info: + Longest register to pin delay is 3.755 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y5_N19; Fanout = 2; REG Node = 'clk_temp'
Info: 2: + IC(0.709 ns) + CELL(3.046 ns) = 3.755 ns; Loc. = PIN_79; Fanout = 0; PIN Node = 'div12'
Info: Total cell delay = 3.046 ns ( 81.12 % )
Info: Total interconnect delay = 0.709 ns ( 18.88 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Mon Mar 26 16:41:45 2007
Info: Elapsed time: 00:00:02
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