ram.map.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 03 10:37:35 2007 " "Info: Processing started: Tue Apr 03 10:37:35 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ram -c ram " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ram -c ram" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram-one " "Info: Found design unit 1: ram-one" {  } { { "ram.vhd" "" { Text "D:/my_eda/ram/ram.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ram " "Info: Found entity 1: ram" {  } { { "ram.vhd" "" { Text "D:/my_eda/ram/ram.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ram " "Info: Elaborating entity \"ram\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "datain ram.vhd(21) " "Warning (10492): VHDL Process Statement warning at ram.vhd(21): signal \"datain\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "ram.vhd" "" { Text "D:/my_eda/ram/ram.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Allocated 134 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 03 10:37:39 2007 " "Info: Processing ended: Tue Apr 03 10:37:39 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IQSYN_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 0 "*******************************************************************" 0 0}
{ "Info" "IQSYN_START_BANNER_PRODUCT" "Partition Merge Quartus II " "Info: Running Quartus II Partition Merge" { { "Info" "IQSYN_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQSYN_START_BANNER_TIME" "Tue Apr 03 10:37:39 2007 " "Info: Processing started: Tue Apr 03 10:37:39 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 0 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "497 " "Info: Implemented 497 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "16 " "Info: Implemented 16 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "473 " "Info: Implemented 473 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQSYN_ERROR_COUNT" "Partition Merge 0 s 0 s Quartus II " "Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings" { { "Info" "IQSYN_END_BANNER_TIME" "Tue Apr 03 10:37:39 2007 " "Info: Processing ended: Tue Apr 03 10:37:39 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQSYN_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}