ram.map.rpt
来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· RPT 代码 · 共 325 行 · 第 1/2 页
RPT
325 行
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |ram ; 473 (473) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 24 ; 0 ; |ram ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+------------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+------------------------------------------------------+---------------------+------------------------+
; data1~120 ; rtl~0 ; yes ;
; data1~112 ; rtl~1 ; yes ;
; data1~104 ; rtl~2 ; yes ;
; data1~128 ; rtl~3 ; yes ;
; data1~80 ; rtl~4 ; yes ;
; data1~88 ; rtl~5 ; yes ;
; data1~72 ; rtl~6 ; yes ;
; data1~96 ; rtl~7 ; yes ;
; data1~56 ; rtl~8 ; yes ;
; data1~48 ; rtl~9 ; yes ;
; data1~40 ; rtl~10 ; yes ;
; data1~64 ; rtl~11 ; yes ;
; data1~144 ; rtl~12 ; yes ;
; data1~152 ; rtl~13 ; yes ;
; data1~136 ; rtl~14 ; yes ;
; data1~160 ; rtl~15 ; yes ;
; data1~216 ; rtl~16 ; yes ;
; data1~248 ; rtl~17 ; yes ;
; data1~184 ; rtl~18 ; yes ;
; data1~280 ; rtl~19 ; yes ;
; data1~240 ; rtl~20 ; yes ;
; data1~208 ; rtl~21 ; yes ;
; data1~176 ; rtl~22 ; yes ;
; data1~272 ; rtl~23 ; yes ;
; data1~200 ; rtl~24 ; yes ;
; data1~232 ; rtl~25 ; yes ;
; data1~168 ; rtl~26 ; yes ;
; data1~264 ; rtl~27 ; yes ;
; data1~256 ; rtl~28 ; yes ;
; data1~224 ; rtl~29 ; yes ;
; data1~192 ; rtl~30 ; yes ;
; data1~288 ; rtl~31 ; yes ;
; data1~89 ; rtl~5 ; yes ;
; data1~81 ; rtl~4 ; yes ;
; data1~73 ; rtl~6 ; yes ;
; data1~97 ; rtl~7 ; yes ;
; data1~113 ; rtl~1 ; yes ;
; data1~121 ; rtl~0 ; yes ;
; data1~105 ; rtl~2 ; yes ;
; data1~129 ; rtl~3 ; yes ;
; data1~49 ; rtl~9 ; yes ;
; data1~57 ; rtl~8 ; yes ;
; data1~41 ; rtl~10 ; yes ;
; data1~65 ; rtl~11 ; yes ;
; data1~153 ; rtl~13 ; yes ;
; data1~145 ; rtl~12 ; yes ;
; data1~137 ; rtl~14 ; yes ;
; data1~161 ; rtl~15 ; yes ;
; data1~209 ; rtl~21 ; yes ;
; data1~241 ; rtl~20 ; yes ;
; data1~177 ; rtl~22 ; yes ;
; data1~273 ; rtl~23 ; yes ;
; data1~249 ; rtl~17 ; yes ;
; data1~217 ; rtl~16 ; yes ;
; data1~185 ; rtl~18 ; yes ;
; data1~281 ; rtl~19 ; yes ;
; data1~233 ; rtl~25 ; yes ;
; data1~201 ; rtl~24 ; yes ;
; data1~169 ; rtl~26 ; yes ;
; data1~265 ; rtl~27 ; yes ;
; data1~225 ; rtl~29 ; yes ;
; data1~257 ; rtl~28 ; yes ;
; data1~193 ; rtl~30 ; yes ;
; data1~289 ; rtl~31 ; yes ;
; data1~122 ; rtl~0 ; yes ;
; data1~114 ; rtl~1 ; yes ;
; data1~106 ; rtl~2 ; yes ;
; data1~130 ; rtl~3 ; yes ;
; data1~82 ; rtl~4 ; yes ;
; data1~90 ; rtl~5 ; yes ;
; data1~74 ; rtl~6 ; yes ;
; data1~98 ; rtl~7 ; yes ;
; data1~58 ; rtl~8 ; yes ;
; data1~50 ; rtl~9 ; yes ;
; data1~42 ; rtl~10 ; yes ;
; data1~66 ; rtl~11 ; yes ;
; data1~146 ; rtl~12 ; yes ;
; data1~154 ; rtl~13 ; yes ;
; data1~138 ; rtl~14 ; yes ;
; data1~162 ; rtl~15 ; yes ;
; data1~218 ; rtl~16 ; yes ;
; data1~250 ; rtl~17 ; yes ;
; data1~186 ; rtl~18 ; yes ;
; data1~282 ; rtl~19 ; yes ;
; data1~242 ; rtl~20 ; yes ;
; data1~210 ; rtl~21 ; yes ;
; data1~178 ; rtl~22 ; yes ;
; data1~274 ; rtl~23 ; yes ;
; data1~202 ; rtl~24 ; yes ;
; data1~234 ; rtl~25 ; yes ;
; data1~170 ; rtl~26 ; yes ;
; data1~266 ; rtl~27 ; yes ;
; data1~258 ; rtl~28 ; yes ;
; data1~226 ; rtl~29 ; yes ;
; data1~194 ; rtl~30 ; yes ;
; data1~290 ; rtl~31 ; yes ;
; data1~91 ; rtl~5 ; yes ;
; data1~83 ; rtl~4 ; yes ;
; data1~75 ; rtl~6 ; yes ;
; data1~99 ; rtl~7 ; yes ;
; Number of user-specified and inferred latches = 256 ; ; ;
+------------------------------------------------------+---------------------+------------------------+
Table restricted to first 100 entries. Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Apr 03 10:37:35 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ram -c ram
Info: Found 2 design units, including 1 entities, in source file ram.vhd
Info: Found design unit 1: ram-one
Info: Found entity 1: ram
Info: Elaborating entity "ram" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at ram.vhd(21): signal "datain" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 134 megabytes of memory during processing
Info: Processing ended: Tue Apr 03 10:37:39 2007
Info: Elapsed time: 00:00:04
Info: *******************************************************************
Info: Running Quartus II Partition Merge
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Apr 03 10:37:39 2007
Info: Implemented 497 device resources after synthesis - the final resource count might be different
Info: Implemented 16 input pins
Info: Implemented 8 output pins
Info: Implemented 473 logic cells
Info: Quartus II Partition Merge was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Apr 03 10:37:39 2007
Info: Elapsed time: 00:00:00
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?