ram.fit.smsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Apr 03 10:37:43 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ram -c ram
Info: Selected device EP2C8T144C8 for design "ram"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 497 of 497 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144C8 is compatible
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS54p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 21 pins of 24 total pins
    Info: Pin dataout[0] not assigned to an exact location on the device
    Info: Pin dataout[1] not assigned to an exact location on the device
    Info: Pin dataout[2] not assigned to an exact location on the device
    Info: Pin dataout[3] not assigned to an exact location on the device
    Info: Pin dataout[4] not assigned to an exact location on the device
    Info: Pin dataout[5] not assigned to an exact location on the device
    Info: Pin dataout[6] not assigned to an exact location on the device
    Info: Pin dataout[7] not assigned to an exact location on the device
    Info: Pin addr[1] not assigned to an exact location on the device
    Info: Pin addr[0] not assigned to an exact location on the device
    Info: Pin rd not assigned to an exact location on the device
    Info: Pin cs not assigned to an exact location on the device
    Info: Pin datain[0] not assigned to an exact location on the device
    Info: Pin wr not assigned to an exact location on the device
    Info: Pin datain[1] not assigned to an exact location on the device
    Info: Pin datain[2] not assigned to an exact location on the device
    Info: Pin datain[3] not assigned to an exact location on the device
    Info: Pin datain[4] not assigned to an exact location on the device
    Info: Pin datain[5] not assigned to an exact location on the device
    Info: Pin datain[6] not assigned to an exact location on the device
    Info: Pin datain[7] not assigned to an exact location on the device
Info: Automatically promoted node rtl~0 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node rtl~1 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node rtl~10 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node rtl~11 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node rtl~12 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node rtl~13 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node rtl~14 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node rtl~15 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 21 (unused VREF, 3.30 VCCIO, 13 input, 8 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  15 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  22 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  18 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Fitter routing operations beginning
Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 4%
    Info: The peak interconnect region extends from location X23_Y10 to location X34_Y19
Info: Fitter routing operations ending: elapsed time is 00:00:03
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 8 output pins without output pin load capacitance assignment
    Info: Pin "dataout[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dataout[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dataout[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dataout[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dataout[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dataout[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dataout[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "dataout[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Delay annotation completed successfully
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
    Info: Allocated 175 megabytes of memory during processing
    Info: Processing ended: Tue Apr 03 10:37:56 2007
    Info: Elapsed time: 00:00:13