mux_llc.tdf

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Cyclone II" IGNORE_CASCADE_BUFFERS="ON" LPM_SIZE=16 LPM_WIDTH=1 LPM_WIDTHS=4 data result sel
--VERSION_BEGIN 7.0 cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ  VERSION_END


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--synthesis_resources = lut 10 
SUBDESIGN mux_llc
( 
	data[15..0]	:	input;
	result[0..0]	:	output;
	sel[3..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_ffs_wire[3..0]	: WIRE;
	sel_node[3..0]	: WIRE;
	w_data64w[3..0]	: WIRE;
	w_data65w[3..0]	: WIRE;
	w_data66w[3..0]	: WIRE;
	w_data67w[3..0]	: WIRE;
	w_data9w[15..0]	: WIRE;
	w_result112w	: WIRE;
	w_result129w	: WIRE;
	w_result145w	: WIRE;
	w_result60w	: WIRE;
	w_result61w	: WIRE;
	w_result62w	: WIRE;
	w_result63w	: WIRE;
	w_result74w	: WIRE;
	w_result95w	: WIRE;
	w_sel68w[1..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( (((w_result61w & sel_node[2..2]) & (! w_result145w)) # (w_result145w & (w_result63w # (! sel_node[2..2])))));
	sel_ffs_wire[] = ( sel[3..0]);
	sel_node[] = ( sel_ffs_wire[3..2], sel[1..0]);
	w_data64w[3..0] = w_data9w[3..0];
	w_data65w[3..0] = w_data9w[7..4];
	w_data66w[3..0] = w_data9w[11..8];
	w_data67w[3..0] = w_data9w[15..12];
	w_data9w[] = ( data[15..0]);
	w_result112w = (((w_data66w[0..0] & (! w_sel68w[1..1])) & (! w_sel68w[0..0])) # (w_sel68w[1..1] & (w_sel68w[0..0] # w_data66w[2..2])));
	w_result129w = (((w_data67w[0..0] & (! w_sel68w[1..1])) & (! w_sel68w[0..0])) # (w_sel68w[1..1] & (w_sel68w[0..0] # w_data67w[2..2])));
	w_result145w = (((w_result60w & (! sel_node[3..3])) & (! sel_node[2..2])) # (sel_node[3..3] & (sel_node[2..2] # w_result62w)));
	w_result60w = (((w_data64w[1..1] & w_sel68w[0..0]) & (! w_result74w)) # (w_result74w & (w_data64w[3..3] # (! w_sel68w[0..0]))));
	w_result61w = (((w_data65w[1..1] & w_sel68w[0..0]) & (! w_result95w)) # (w_result95w & (w_data65w[3..3] # (! w_sel68w[0..0]))));
	w_result62w = (((w_data66w[1..1] & w_sel68w[0..0]) & (! w_result112w)) # (w_result112w & (w_data66w[3..3] # (! w_sel68w[0..0]))));
	w_result63w = (((w_data67w[1..1] & w_sel68w[0..0]) & (! w_result129w)) # (w_result129w & (w_data67w[3..3] # (! w_sel68w[0..0]))));
	w_result74w = (((w_data64w[0..0] & (! w_sel68w[1..1])) & (! w_sel68w[0..0])) # (w_sel68w[1..1] & (w_sel68w[0..0] # w_data64w[2..2])));
	w_result95w = (((w_data65w[0..0] & (! w_sel68w[1..1])) & (! w_sel68w[0..0])) # (w_sel68w[1..1] & (w_sel68w[0..0] # w_data65w[2..2])));
	w_sel68w[1..0] = sel_node[1..0];
END;
--VALID FILE