cnt16.tan.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 8.698 ns   ; q[1]~reg0 ; co   ; clk        ;
; N/A   ; None         ; 8.307 ns   ; q[0]~reg0 ; co   ; clk        ;
; N/A   ; None         ; 8.191 ns   ; q[2]~reg0 ; co   ; clk        ;
; N/A   ; None         ; 7.625 ns   ; q[3]~reg0 ; co   ; clk        ;
; N/A   ; None         ; 7.499 ns   ; q[0]~reg0 ; q[0] ; clk        ;
; N/A   ; None         ; 7.477 ns   ; q[1]~reg0 ; q[1] ; clk        ;
; N/A   ; None         ; 7.309 ns   ; q[2]~reg0 ; q[2] ; clk        ;
; N/A   ; None         ; 7.298 ns   ; q[3]~reg0 ; q[3] ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 6.380 ns        ; en   ; co ;
+-------+-------------------+-----------------+------+----+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; 0.614 ns  ; d[0] ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -0.508 ns ; en   ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -0.985 ns ; en   ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -1.071 ns ; en   ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -1.157 ns ; en   ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -4.443 ns ; d[1] ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -4.458 ns ; d[3] ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -4.937 ns ; s    ; q[0]~reg0 ; clk      ;
; N/A           ; None        ; -4.937 ns ; s    ; q[1]~reg0 ; clk      ;
; N/A           ; None        ; -4.937 ns ; s    ; q[2]~reg0 ; clk      ;
; N/A           ; None        ; -4.937 ns ; s    ; q[3]~reg0 ; clk      ;
; N/A           ; None        ; -5.116 ns ; d[2] ; q[2]~reg0 ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Mar 09 22:21:05 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cnt16 -c cnt16 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 340.02 MHz between source register "q[0]~reg0" and destination register "q[3]~reg0"
    Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.825 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 4; REG Node = 'q[0]~reg0'
            Info: 2: + IC(0.443 ns) + CELL(0.596 ns) = 1.039 ns; Loc. = LCCOMB_X1_Y6_N18; Fanout = 2; COMB Node = 'q[0]~52'
            Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.125 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 2; COMB Node = 'q[1]~53'
            Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.211 ns; Loc. = LCCOMB_X1_Y6_N22; Fanout = 1; COMB Node = 'q[2]~54'
            Info: 5: + IC(0.000 ns) + CELL(0.506 ns) = 1.717 ns; Loc. = LCCOMB_X1_Y6_N24; Fanout = 1; COMB Node = 'q[3]~51'
            Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 1.825 ns; Loc. = LCFF_X1_Y6_N25; Fanout = 3; REG Node = 'q[3]~reg0'
            Info: Total cell delay = 1.382 ns ( 75.73 % )
            Info: Total interconnect delay = 0.443 ns ( 24.27 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.801 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N25; Fanout = 3; REG Node = 'q[3]~reg0'
                Info: Total cell delay = 1.756 ns ( 62.69 % )
                Info: Total interconnect delay = 1.045 ns ( 37.31 % )
            Info: - Longest clock path from clock "clk" to source register is 2.801 ns
                Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 4; REG Node = 'q[0]~reg0'
                Info: Total cell delay = 1.756 ns ( 62.69 % )
                Info: Total interconnect delay = 1.045 ns ( 37.31 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "q[2]~reg0" (data pin = "d[2]", clock pin = "clk") is 5.382 ns
    Info: + Longest pin to register delay is 8.223 ns
        Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_79; Fanout = 1; PIN Node = 'd[2]'
        Info: 2: + IC(6.828 ns) + CELL(0.460 ns) = 8.223 ns; Loc. = LCFF_X1_Y6_N23; Fanout = 4; REG Node = 'q[2]~reg0'
        Info: Total cell delay = 1.395 ns ( 16.96 % )
        Info: Total interconnect delay = 6.828 ns ( 83.04 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.801 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N23; Fanout = 4; REG Node = 'q[2]~reg0'
        Info: Total cell delay = 1.756 ns ( 62.69 % )
        Info: Total interconnect delay = 1.045 ns ( 37.31 % )
Info: tco from clock "clk" to destination pin "co" through register "q[1]~reg0" is 8.698 ns
    Info: + Longest clock path from clock "clk" to source register is 2.801 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'q[1]~reg0'
        Info: Total cell delay = 1.756 ns ( 62.69 % )
        Info: Total interconnect delay = 1.045 ns ( 37.31 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.593 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'q[1]~reg0'
        Info: 2: + IC(0.750 ns) + CELL(0.589 ns) = 1.339 ns; Loc. = LCCOMB_X1_Y6_N0; Fanout = 1; COMB Node = 'co~30'
        Info: 3: + IC(0.355 ns) + CELL(0.206 ns) = 1.900 ns; Loc. = LCCOMB_X1_Y6_N12; Fanout = 1; COMB Node = 'co~0'
        Info: 4: + IC(0.637 ns) + CELL(3.056 ns) = 5.593 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'co'
        Info: Total cell delay = 3.851 ns ( 68.85 % )
        Info: Total interconnect delay = 1.742 ns ( 31.15 % )
Info: Longest tpd from source pin "en" to destination pin "co" is 6.380 ns
    Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_21; Fanout = 3; PIN Node = 'en'
    Info: 2: + IC(1.008 ns) + CELL(0.589 ns) = 2.687 ns; Loc. = LCCOMB_X1_Y6_N12; Fanout = 1; COMB Node = 'co~0'
    Info: 3: + IC(0.637 ns) + CELL(3.056 ns) = 6.380 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'co'
    Info: Total cell delay = 4.735 ns ( 74.22 % )
    Info: Total interconnect delay = 1.645 ns ( 25.78 % )
Info: th for register "q[0]~reg0" (data pin = "d[0]", clock pin = "clk") is 0.614 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.801 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.801 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.756 ns ( 62.69 % )
        Info: Total interconnect delay = 1.045 ns ( 37.31 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 2.493 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_22; Fanout = 1; PIN Node = 'd[0]'
        Info: 2: + IC(0.933 ns) + CELL(0.460 ns) = 2.493 ns; Loc. = LCFF_X1_Y6_N19; Fanout = 4; REG Node = 'q[0]~reg0'
        Info: Total cell delay = 1.560 ns ( 62.58 % )
        Info: Total interconnect delay = 0.933 ns ( 37.42 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Mar 09 22:21:06 2007
    Info: Elapsed time: 00:00:02