cnt16.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt16 is
port(clk,r,s,en:in std_logic;
     d:in std_logic_vector(3 downto 0);
     co:out std_logic;
     q:buffer std_logic_vector(3 downto 0));
end;
architecture one of cnt16 is
begin
process(clk,r)
begin
if r='1' then
	q<=(others=>'0');
elsif clk'event and clk='1' then
	if s='1' then
		q<=d;
	elsif en='1' then
		q<=q+1;
	else 
		q<=q;
	end if;
end if;
end process;
co<='1' when q="1111" and en='1' else '0';
end;