div7.map.summary

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Analysis & Synthesis Status : Successful - Mon Mar 26 20:03:34 2007
Quartus II Version : 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
Revision Name : div7
Top-level Entity Name : div7
Family : Cyclone II
Total logic elements : 4
Total registers : 4
Total pins : 2
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0