half_sub.qsf

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		half_sub_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8T144C8
set_global_assignment -name TOP_LEVEL_ENTITY half_sub
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:04:14  MARCH 07, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION OFF -section_id eda_simulation
set_global_assignment -name EDA_FLATTEN_BUSES OFF -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_FILE_NAME "G:/eda_1/random signal/simulation/modelsim/random_signal.vht" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME ty -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME i1 -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_RUN_FOR "100 ns" -section_id eda_simulation
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name VHDL_FILE half_sub.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE half_sub.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name VECTOR_INPUT_SOURCE half_sub.vwf
set_global_assignment -name BDF_FILE Block1.bdf