half_sub_1.fit.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Fitter report for half_sub_1
Wed Mar 07 14:27:43 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Non-Global High Fan-Out Signals
 15. Interconnect Usage Summary
 16. LAB Logic Elements
 17. LAB Signals Sourced
 18. LAB Signals Sourced Out
 19. LAB Distinct Inputs
 20. Fitter Device Options
 21. Fitter Messages
 22. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Fitter Summary                                                                     ;
+------------------------------------+-----------------------------------------------+
; Fitter Status                      ; Successful - Wed Mar 07 14:27:43 2007         ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1 SJ Full Version ;
; Revision Name                      ; half_sub_1                                    ;
; Top-level Entity Name              ; half_sub_1                                    ;
; Family                             ; Cyclone II                                    ;
; Device                             ; EP2C8T144C8                                   ;
; Timing Models                      ; Final                                         ;
; Total logic elements               ; 2 / 8,256 ( < 1 % )                           ;
; Total registers                    ; 0                                             ;
; Total pins                         ; 4 / 85 ( 5 % )                                ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 0 / 165,888 ( 0 % )                           ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % )                                ;
; Total PLLs                         ; 0 / 2 ( 0 % )                                 ;
+------------------------------------+-----------------------------------------------+


+------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                  ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Option                                         ; Setting                        ; Default Value                  ;
+------------------------------------------------+--------------------------------+--------------------------------+
; Device                                         ; EP2C8T144C8                    ;                                ;
; Use smart compilation                          ; Off                            ; Off                            ;
; Router Timing Optimization Level               ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                    ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                       ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                           ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                    ; Off                            ; Off                            ;
; PowerPlay Power Optimization                   ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing     ; On                             ; On                             ;
; Limit to One Fitting Attempt                   ; Off                            ; Off                            ;
; Final Placement Optimizations                  ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations    ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                  ; 1                              ; 1                              ;
; PCI I/O                                        ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                          ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                      ; Off                            ; Off                            ;
; Auto Global Memory Control Signals             ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/Cyclone II ; Auto                           ; Auto                           ;
; Auto Delay Chains                              ; On                             ; On                             ;
; Auto Merge PLLs                                ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs              ; Off                            ; Off                            ;
; Fitter Effort                                  ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                ; Normal                         ; Normal                         ;
; Auto Global Clock                              ; On                             ; On                             ;
; Auto Global Register Control Signals           ; On                             ; On                             ;
; Always Enable Input Buffers                    ; Off                            ; Off                            ;
+------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/my_eda/half_sub/half_sub_1.pin.


+-------------------------------------------------------------------+
; Fitter Resource Usage Summary                                     ;
+---------------------------------------------+---------------------+
; Resource                                    ; Usage               ;
+---------------------------------------------+---------------------+
; Total logic elements                        ; 2 / 8,256 ( < 1 % ) ;
;     -- Combinational with no register       ; 2                   ;
;     -- Register only                        ; 0                   ;
;     -- Combinational with a register        ; 0                   ;
;                                             ;                     ;
; Logic element usage by number of LUT inputs ;                     ;
;     -- 4 input functions                    ; 0                   ;
;     -- 3 input functions                    ; 0                   ;
;     -- <=2 input functions                  ; 2                   ;
;     -- Register only                        ; 0                   ;
;                                             ;                     ;
; Logic elements by mode                      ;                     ;
;     -- normal mode                          ; 2                   ;
;     -- arithmetic mode                      ; 0                   ;
;                                             ;                     ;
; Total registers                             ; 0 / 8,256 ( 0 % )   ;
; Total LABs                                  ; 1 / 516 ( < 1 % )   ;
; User inserted logic elements                ; 0                   ;
; Virtual pins                                ; 0                   ;
; I/O pins                                    ; 4 / 85 ( 5 % )      ;
;     -- Clock pins                           ; 0 / 4 ( 0 % )       ;
; Global signals                              ; 0                   ;
; M4Ks                                        ; 0 / 36 ( 0 % )      ;
; Total memory bits                           ; 0 / 165,888 ( 0 % ) ;
; Total RAM block bits                        ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 36 ( 0 % )      ;