half_sub_1.vhd

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· VHDL 代码 · 共 14 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity half_sub_1 is
port(a,b:in std_logic;
     dout,cout:out std_logic);
end;
architecture one of half_sub_1 is
signal temp:std_logic_vector(1 downto 0);
begin
temp<=('0'&a)-b;
dout<=temp(0);
cout<=temp(1);
end;