half_sub.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity half_sub is
port(a:in std_logic;
     b:in std_logic;
     dout:out std_logic;
     cout:out std_logic);
end;
architecture one of half_sub is
begin
dout<=a xor b;
cout<=not a and b;
end;