yb_cnt4.qws

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· QWS 代码 · 共 28 行

[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=yb_cnt4.vwf
DocumentCLSID={4a9ed22a-e60b-11d1-a0bd-0020affa43f2}
WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPAAAAAAAAAAAAAAAABHCAAAAAGEBAAAAA
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
AFC_SIM_AP_NAME=yb_cnt4
AFC_PROJ_DB_PATH=D:/my_eda/yb_cnt4/db/yb_cnt4.quartus_db
AFC_IN_REPORT=False
[ProjectWorkspace.Frames.ChildFrames.Document-1]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
DocPathName=yb_cnt4.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
WindowPlacement=MCAAAAAACAAAAAAADAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPCOPPPPPPIFAAAAAAEHAAAAAAGOCAAAAAGLBAAAAA
IsActiveChildFrame=True
ptn_Child1=StateMap