demux4.hier_info

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· HIER_INFO 代码 · 共 20 行

|demux4
din => Mux0.IN3
din => Mux1.IN3
din => Mux2.IN3
din => Mux3.IN3
a[0] => Mux0.IN5
a[0] => Mux1.IN5
a[0] => Mux2.IN5
a[0] => Mux3.IN5
a[1] => Mux0.IN4
a[1] => Mux1.IN4
a[1] => Mux2.IN4
a[1] => Mux3.IN4
y0 <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
y1 <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
y2 <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
y3 <= Mux3.DB_MAX_OUTPUT_PORT_TYPE