add.fit.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 11 行

I/O Assignment Analysis Status : Successful - Sat May 12 22:53:25 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : add
Top-level Entity Name : add
Family : Cyclone II
Device : EP2C8T144C8
Timing Models : Final
Total pins : 0 / 85 ( 0 % )
Total virtual pins : 0
Total PLLs : 0 / 2 ( 0 % )