yb_cnt16.map.rpt

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· RPT 代码 · 共 224 行 · 第 1/2 页

; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                 ;
+----------------------------------+-----------------+-----------------+---------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path    ;
+----------------------------------+-----------------+-----------------+---------------------------------+
; yb_cnt16.vhd                     ; yes             ; User VHDL File  ; D:/my_eda/yb_cnt16/yb_cnt16.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 4     ;
; Total combinational functions               ; 4     ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- <=2 input functions                  ; 4     ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 4     ;
;     -- arithmetic mode                      ; 0     ;
; Total registers                             ; 4     ;
; I/O pins                                    ; 6     ;
; Maximum fan-out node                        ; rst   ;
; Maximum fan-out                             ; 4     ;
; Total fan-out                               ; 20    ;
; Average fan-out                             ; 1.43  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                            ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name            ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------------+
; |yb_cnt16                  ; 4 (0)             ; 4 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 6    ; 0            ; |yb_cnt16                      ;
;    |yb_dff:\l1:0:yb_dffx|  ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |yb_cnt16|yb_dff:\l1:0:yb_dffx ;
;    |yb_dff:\l1:1:yb_dffx|  ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |yb_cnt16|yb_dff:\l1:1:yb_dffx ;
;    |yb_dff:\l1:2:yb_dffx|  ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |yb_cnt16|yb_dff:\l1:2:yb_dffx ;
;    |yb_dff:\l1:3:yb_dffx|  ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |yb_cnt16|yb_dff:\l1:3:yb_dffx ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+--------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; yb_dff:\l1:0:yb_dffx|qn                ; 3       ;
; yb_dff:\l1:1:yb_dffx|qn                ; 3       ;
; yb_dff:\l1:2:yb_dffx|qn                ; 3       ;
; yb_dff:\l1:3:yb_dffx|qn                ; 2       ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Mar 12 22:01:35 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off yb_cnt16 -c yb_cnt16
Info: Found 4 design units, including 2 entities, in source file yb_cnt16.vhd
    Info: Found design unit 1: yb_dff-one
    Info: Found design unit 2: yb_cnt16-one
    Info: Found entity 1: yb_dff
    Info: Found entity 2: yb_cnt16
Info: Elaborating entity "yb_cnt16" for the top level hierarchy
Info: Elaborating entity "yb_dff" for hierarchy "yb_dff:\l1:0:yb_dffx"
Info: Duplicate registers merged to single register
    Info: Duplicate register "yb_dff:\l1:3:yb_dffx|q" merged to single register "yb_dff:\l1:3:yb_dffx|qn", power-up level changed
    Info: Duplicate register "yb_dff:\l1:2:yb_dffx|q" merged to single register "yb_dff:\l1:2:yb_dffx|qn", power-up level changed
    Info: Duplicate register "yb_dff:\l1:1:yb_dffx|q" merged to single register "yb_dff:\l1:1:yb_dffx|qn", power-up level changed
    Info: Duplicate register "yb_dff:\l1:0:yb_dffx|q" merged to single register "yb_dff:\l1:0:yb_dffx|qn", power-up level changed
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 10 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 4 output pins
    Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Mar 12 22:01:38 2007
    Info: Elapsed time: 00:00:05