mchange_1.vhd

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mchange_1 is
port(clk:in std_logic;
     clr:in std_logic;
     m:in integer range 0 to 99;
     q:buffer integer range 0 to 99);
end;
architecture one of mchange_1 is
signal md:integer range 0 to 99;
begin
process(clk,clr,m)
begin
md<=m-1;
if clr='1' then  q<=0;
elsif clk'event and clk='1' then 
	if q=md then q<=0;
	else q<=q+1;
	end if;
end if;
end process;
end;