nand_2.map.qmsg

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· QMSG 代码 · 共 9 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 12 20:47:07 2007 " "Info: Processing started: Mon Feb 12 20:47:07 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off nand_2 -c nand_2 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off nand_2 -c nand_2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nand_2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file nand_2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 nand_2-one " "Info: Found design unit 1: nand_2-one" {  } { { "nand_2.vhd" "" { Text "D:/my_eda/nand/nand2/nand_2.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 nand_2 " "Info: Found entity 1: nand_2" {  } { { "nand_2.vhd" "" { Text "D:/my_eda/nand/nand2/nand_2.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../nand_2_1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../nand_2_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 nand_2_1-one " "Info: Found design unit 1: nand_2_1-one" {  } { { "../nand_2_1.vhd" "" { Text "D:/my_eda/nand/nand_2_1.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 nand_2_1 " "Info: Found entity 1: nand_2_1" {  } { { "../nand_2_1.vhd" "" { Text "D:/my_eda/nand/nand_2_1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "nand_2 " "Info: Elaborating entity \"nand_2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "4 " "Info: Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "1 " "Info: Implemented 1 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 12 20:47:09 2007 " "Info: Processing ended: Mon Feb 12 20:47:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}