jk.tan.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.233 ns
From           : s
To             : qn_temp~_emulated
From Clock     : --
To Clock       : cp
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.152 ns
From           : q_temp~_emulated
To             : q
From Clock     : cp
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.055 ns
From           : s
To             : q
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.902 ns
From           : j
To             : q_temp~_emulated
From Clock     : --
To Clock       : cp
Failed Paths   : 0

Type           : Clock Setup: 'cp'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 340.02 MHz ( period = 2.941 ns )
From           : q_temp~_emulated
To             : q_temp~_emulated
From Clock     : cp
To Clock       : cp
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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