jk.tan.qmsg

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 27 20:54:03 2007 " "Info: Processing started: Sun May 27 20:54:03 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Jk -c Jk --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Jk -c Jk --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "q_temp~34 " "Warning: Node \"q_temp~34\" is a latch" {  } { { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "qn_temp~24 " "Warning: Node \"qn_temp~24\" is a latch" {  } { { "Jk.vhd" "" { Text "D:/my_eda/Jk/Jk.vhd" 13 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}