jk.vhd

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· VHDL 代码 · 共 39 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity JK is
port(j,k,r,s,cp:in std_logic;
     q,qn: out std_logic);
end;
architecture one of Jk is
signal q_temp,qn_temp:std_logic;
begin
process(j,k,cp,r,s,q_temp,qn_temp)
begin
if r='0' and s='1' then
	q_temp<='0';
	qn_temp<='1';
elsif r='1' and s='0' then 
	q_temp<='1';
	qn_temp<='0';
elsif r='0' and s='0' then
	q_temp<=q_temp;
	qn_temp<=qn_temp;
elsif cp'event and cp='1' then
	if j='0' and k='1' then
	    q_temp<='0';
		qn_temp<='1';
	elsif j='1' and k='0' then
	    q_temp<='1';
		qn_temp<='0';
	elsif j='1' and k='1' then
	    q_temp<=not q_temp;
		qn_temp<=not qn_temp;
	end if;
end if;
end process;
q<=q_temp;
qn<=qn_temp;
end;