jk_1.map.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Sun May 27 14:39:46 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : jk_1
Top-level Entity Name : jk_1
Family : Cyclone II
Total logic elements : 4
    Total combinational functions : 4
    Dedicated logic registers : 1
Total registers : 1
Total pins : 6
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0