div5_1.tan.qmsg

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "8 " "Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cnt2\[1\] " "Info: Detected ripple clock \"cnt2\[1\]\" as buffer" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[0\] " "Info: Detected ripple clock \"cnt2\[0\]\" as buffer" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[1\] " "Info: Detected ripple clock \"cnt1\[1\]\" as buffer" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[2\] " "Info: Detected ripple clock \"cnt1\[2\]\" as buffer" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "out_temp~68 " "Info: Detected gated clock \"out_temp~68\" as buffer" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "out_temp~68" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt1\[0\] " "Info: Detected ripple clock \"cnt1\[0\]\" as buffer" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 18 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt2\[2\] " "Info: Detected ripple clock \"cnt2\[2\]\" as buffer" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 28 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt2\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "out_temp~69 " "Info: Detected gated clock \"out_temp~69\" as buffer" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } } { "e:/altera60/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera60/quartus60/win/Assignment Editor.qase" 1 { { 0 "out_temp~69" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register div5~reg0 div5~reg0 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"div5~reg0\" and destination register \"div5~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Longest register register " "Info: + Longest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div5~reg0 1 REG LCFF_X4_Y3_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns div5~4 2 COMB LCCOMB_X4_Y3_N18 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X4_Y3_N18; Fanout = 1; COMB Node = 'div5~4'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { div5~reg0 div5~4 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns div5~reg0 3 REG LCFF_X4_Y3_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { div5~4 div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { div5~reg0 div5~4 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { div5~reg0 div5~4 div5~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.090 ns - Smallest " "Info: - Smallest clock skew is -1.090 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.834 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.705 ns) + CELL(0.787 ns) 2.603 ns cnt1\[2\] 3 REG LCFF_X4_Y3_N23 3 " "Info: 3: + IC(0.705 ns) + CELL(0.787 ns) = 2.603 ns; Loc. = LCFF_X4_Y3_N23; Fanout = 3; REG Node = 'cnt1\[2\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.492 ns" { clk~clkctrl cnt1[2] } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.307 ns) + CELL(0.150 ns) 3.060 ns out_temp~69 4 COMB LCCOMB_X4_Y3_N8 1 " "Info: 4: + IC(0.307 ns) + CELL(0.150 ns) = 3.060 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.457 ns" { cnt1[2] out_temp~69 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.237 ns) + CELL(0.537 ns) 3.834 ns div5~reg0 5 REG LCFF_X4_Y3_N19 2 " "Info: 5: + IC(0.237 ns) + CELL(0.537 ns) = 3.834 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.774 ns" { out_temp~69 div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.463 ns ( 64.24 % ) " "Info: Total cell delay = 2.463 ns ( 64.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.371 ns ( 35.76 % ) " "Info: Total interconnect delay = 1.371 ns ( 35.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.834 ns" { clk clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.834 ns" { clk clk~combout clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.705ns 0.307ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.150ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.924 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 4.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.787 ns) 2.600 ns cnt2\[0\] 3 REG LCFF_X4_Y4_N27 4 " "Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X4_Y4_N27; Fanout = 4; REG Node = 'cnt2\[0\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl cnt2[0] } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.275 ns) 3.626 ns out_temp~68 4 COMB LCCOMB_X4_Y3_N20 1 " "Info: 4: + IC(0.751 ns) + CELL(0.275 ns) = 3.626 ns; Loc. = LCCOMB_X4_Y3_N20; Fanout = 1; COMB Node = 'out_temp~68'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.026 ns" { cnt2[0] out_temp~68 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.249 ns) + CELL(0.275 ns) 4.150 ns out_temp~69 5 COMB LCCOMB_X4_Y3_N8 1 " "Info: 5: + IC(0.249 ns) + CELL(0.275 ns) = 4.150 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.524 ns" { out_temp~68 out_temp~69 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.237 ns) + CELL(0.537 ns) 4.924 ns div5~reg0 6 REG LCFF_X4_Y3_N19 2 " "Info: 6: + IC(0.237 ns) + CELL(0.537 ns) = 4.924 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.774 ns" { out_temp~69 div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.863 ns ( 58.14 % ) " "Info: Total cell delay = 2.863 ns ( 58.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.061 ns ( 41.86 % ) " "Info: Total interconnect delay = 2.061 ns ( 41.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.924 ns" { clk clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.924 ns" { clk clk~combout clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns 0.751ns 0.249ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.275ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.834 ns" { clk clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.834 ns" { clk clk~combout clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.705ns 0.307ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.150ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.924 ns" { clk clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.924 ns" { clk clk~combout clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns 0.751ns 0.249ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.275ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { div5~reg0 div5~4 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { div5~reg0 div5~4 div5~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.834 ns" { clk clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.834 ns" { clk clk~combout clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.705ns 0.307ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.150ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.924 ns" { clk clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.924 ns" { clk clk~combout clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns 0.751ns 0.249ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.275ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { div5~reg0 } {  } {  } } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "div5~reg0 div5~reg0 clk 699 ps " "Info: Found hold time violation between source  pin or register \"div5~reg0\" and destination pin or register \"div5~reg0\" for clock \"clk\" (Hold time is 699 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.090 ns + Largest " "Info: + Largest clock skew is 1.090 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.924 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 4.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.787 ns) 2.600 ns cnt2\[0\] 3 REG LCFF_X4_Y4_N27 4 " "Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X4_Y4_N27; Fanout = 4; REG Node = 'cnt2\[0\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl cnt2[0] } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.275 ns) 3.626 ns out_temp~68 4 COMB LCCOMB_X4_Y3_N20 1 " "Info: 4: + IC(0.751 ns) + CELL(0.275 ns) = 3.626 ns; Loc. = LCCOMB_X4_Y3_N20; Fanout = 1; COMB Node = 'out_temp~68'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.026 ns" { cnt2[0] out_temp~68 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.249 ns) + CELL(0.275 ns) 4.150 ns out_temp~69 5 COMB LCCOMB_X4_Y3_N8 1 " "Info: 5: + IC(0.249 ns) + CELL(0.275 ns) = 4.150 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.524 ns" { out_temp~68 out_temp~69 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.237 ns) + CELL(0.537 ns) 4.924 ns div5~reg0 6 REG LCFF_X4_Y3_N19 2 " "Info: 6: + IC(0.237 ns) + CELL(0.537 ns) = 4.924 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.774 ns" { out_temp~69 div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.863 ns ( 58.14 % ) " "Info: Total cell delay = 2.863 ns ( 58.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.061 ns ( 41.86 % ) " "Info: Total interconnect delay = 2.061 ns ( 41.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.924 ns" { clk clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.924 ns" { clk clk~combout clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns 0.751ns 0.249ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.275ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.834 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.705 ns) + CELL(0.787 ns) 2.603 ns cnt1\[2\] 3 REG LCFF_X4_Y3_N23 3 " "Info: 3: + IC(0.705 ns) + CELL(0.787 ns) = 2.603 ns; Loc. = LCFF_X4_Y3_N23; Fanout = 3; REG Node = 'cnt1\[2\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "1.492 ns" { clk~clkctrl cnt1[2] } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.307 ns) + CELL(0.150 ns) 3.060 ns out_temp~69 4 COMB LCCOMB_X4_Y3_N8 1 " "Info: 4: + IC(0.307 ns) + CELL(0.150 ns) = 3.060 ns; Loc. = LCCOMB_X4_Y3_N8; Fanout = 1; COMB Node = 'out_temp~69'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.457 ns" { cnt1[2] out_temp~69 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.237 ns) + CELL(0.537 ns) 3.834 ns div5~reg0 5 REG LCFF_X4_Y3_N19 2 " "Info: 5: + IC(0.237 ns) + CELL(0.537 ns) = 3.834 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.774 ns" { out_temp~69 div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.463 ns ( 64.24 % ) " "Info: Total cell delay = 2.463 ns ( 64.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.371 ns ( 35.76 % ) " "Info: Total interconnect delay = 1.371 ns ( 35.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.834 ns" { clk clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.834 ns" { clk clk~combout clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.705ns 0.307ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.150ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.924 ns" { clk clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.924 ns" { clk clk~combout clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns 0.751ns 0.249ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.275ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.834 ns" { clk clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.834 ns" { clk clk~combout clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.705ns 0.307ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.150ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns - Shortest register register " "Info: - Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div5~reg0 1 REG LCFF_X4_Y3_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns div5~4 2 COMB LCCOMB_X4_Y3_N18 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X4_Y3_N18; Fanout = 1; COMB Node = 'div5~4'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { div5~reg0 div5~4 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns div5~reg0 3 REG LCFF_X4_Y3_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X4_Y3_N19; Fanout = 2; REG Node = 'div5~reg0'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { div5~4 div5~reg0 } "NODE_NAME" } } { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { div5~reg0 div5~4 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { div5~reg0 div5~4 div5~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "div5_1.vhd" "" { Text "D:/my_eda/div5_1/div5_1.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "4.924 ns" { clk clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "4.924 ns" { clk clk~combout clk~clkctrl cnt2[0] out_temp~68 out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns 0.751ns 0.249ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.275ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "3.834 ns" { clk clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "3.834 ns" { clk clk~combout clk~clkctrl cnt1[2] out_temp~69 div5~reg0 } { 0.000ns 0.000ns 0.122ns 0.705ns 0.307ns 0.237ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.150ns 0.537ns } } } { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { div5~reg0 div5~4 div5~reg0 } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { div5~reg0 div5~4 div5~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}