latch8_1.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity latch8_1 is
port(d:in std_logic_vector(7 downto 0);  ----数据输入
     oe:in std_logic;                 ----三态控制端口
     g:in std_logic;                ----时钟输入
     q:out std_logic_vector(7 downto 0));----数据输出
end;
architecture one of latch8_1 is
signal q_temp:std_logic_vector(7 downto 0);
begin
process(g,oe,d)
begin
if oe='0' then
	   if g='1' then
	   q_temp<=d;
	end if;
else q_temp<="ZZZZZZZZ";
end if;
end process;
q<=q_temp;
end;