latch8_1.tan.rpt

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· RPT 代码 · 共 198 行

Timing Analyzer report for latch8_1
Sat Mar 17 14:50:18 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. tsu
  6. tco
  7. th
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
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and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                           ;
+------------------------------+-------+---------------+-------------+-----------+-----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From      ; To        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-----------+-----------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 6.413 ns    ; d[1]      ; q_temp[1] ; --         ; g        ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.785 ns    ; q_temp[3] ; q[3]      ; g          ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -1.596 ns   ; d[7]      ; q_temp[7] ; --         ; g        ; 0            ;
; Total number of failed paths ;       ;               ;             ;           ;           ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-----------+-----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; g               ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------+
; tsu                                                             ;
+-------+--------------+------------+------+-----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To        ; To Clock ;
+-------+--------------+------------+------+-----------+----------+
; N/A   ; None         ; 6.413 ns   ; d[1] ; q_temp[1] ; g        ;
; N/A   ; None         ; 6.338 ns   ; d[0] ; q_temp[0] ; g        ;
; N/A   ; None         ; 6.269 ns   ; d[3] ; q_temp[3] ; g        ;
; N/A   ; None         ; 5.948 ns   ; d[2] ; q_temp[2] ; g        ;
; N/A   ; None         ; 2.892 ns   ; d[6] ; q_temp[6] ; g        ;
; N/A   ; None         ; 2.882 ns   ; d[4] ; q_temp[4] ; g        ;
; N/A   ; None         ; 2.570 ns   ; d[5] ; q_temp[5] ; g        ;
; N/A   ; None         ; 2.554 ns   ; d[7] ; q_temp[7] ; g        ;
+-------+--------------+------------+------+-----------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 7.785 ns   ; q_temp[3] ; q[3] ; g          ;
; N/A   ; None         ; 7.606 ns   ; q_temp[1] ; q[1] ; g          ;
; N/A   ; None         ; 7.574 ns   ; q_temp[0] ; q[0] ; g          ;
; N/A   ; None         ; 7.475 ns   ; q_temp[6] ; q[6] ; g          ;
; N/A   ; None         ; 7.431 ns   ; q_temp[7] ; q[7] ; g          ;
; N/A   ; None         ; 7.006 ns   ; q_temp[5] ; q[5] ; g          ;
; N/A   ; None         ; 6.589 ns   ; q_temp[2] ; q[2] ; g          ;
; N/A   ; None         ; 6.582 ns   ; q_temp[4] ; q[4] ; g          ;
+-------+--------------+------------+-----------+------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -1.596 ns ; d[7] ; q_temp[7] ; g        ;
; N/A           ; None        ; -1.612 ns ; d[5] ; q_temp[5] ; g        ;
; N/A           ; None        ; -1.680 ns ; d[4] ; q_temp[4] ; g        ;
; N/A           ; None        ; -1.685 ns ; d[6] ; q_temp[6] ; g        ;
; N/A           ; None        ; -4.991 ns ; d[2] ; q_temp[2] ; g        ;
; N/A           ; None        ; -5.063 ns ; d[3] ; q_temp[3] ; g        ;
; N/A           ; None        ; -5.136 ns ; d[0] ; q_temp[0] ; g        ;
; N/A           ; None        ; -5.455 ns ; d[1] ; q_temp[1] ; g        ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Mar 17 14:50:17 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off latch8_1 -c latch8_1 --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "q_temp[0]" is a latch
    Warning: Node "comb_53" is a latch
    Warning: Node "q_temp[1]" is a latch
    Warning: Node "q_temp[2]" is a latch
    Warning: Node "q_temp[3]" is a latch
    Warning: Node "q_temp[4]" is a latch
    Warning: Node "q_temp[5]" is a latch
    Warning: Node "q_temp[6]" is a latch
    Warning: Node "q_temp[7]" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "g" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: tsu for register "q_temp[1]" (data pin = "d[1]", clock pin = "g") is 6.413 ns
    Info: + Longest pin to register delay is 8.305 ns
        Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_51; Fanout = 1; PIN Node = 'd[1]'
        Info: 2: + IC(6.745 ns) + CELL(0.616 ns) = 8.305 ns; Loc. = LCCOMB_X1_Y8_N14; Fanout = 1; REG Node = 'q_temp[1]'
        Info: Total cell delay = 1.560 ns ( 18.78 % )
        Info: Total interconnect delay = 6.745 ns ( 81.22 % )
    Info: + Micro setup delay of destination is 0.958 ns
    Info: - Shortest clock path from clock "g" to destination register is 2.850 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'g'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'g~clkctrl'
        Info: 3: + IC(1.415 ns) + CELL(0.206 ns) = 2.850 ns; Loc. = LCCOMB_X1_Y8_N14; Fanout = 1; REG Node = 'q_temp[1]'
        Info: Total cell delay = 1.296 ns ( 45.47 % )
        Info: Total interconnect delay = 1.554 ns ( 54.53 % )
Info: tco from clock "g" to destination pin "q[3]" through register "q_temp[3]" is 7.785 ns
    Info: + Longest clock path from clock "g" to source register is 2.851 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'g'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'g~clkctrl'
        Info: 3: + IC(1.416 ns) + CELL(0.206 ns) = 2.851 ns; Loc. = LCCOMB_X1_Y8_N4; Fanout = 1; REG Node = 'q_temp[3]'
        Info: Total cell delay = 1.296 ns ( 45.46 % )
        Info: Total interconnect delay = 1.555 ns ( 54.54 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.934 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X1_Y8_N4; Fanout = 1; REG Node = 'q_temp[3]'
        Info: 2: + IC(1.698 ns) + CELL(3.236 ns) = 4.934 ns; Loc. = PIN_42; Fanout = 0; PIN Node = 'q[3]'
        Info: Total cell delay = 3.236 ns ( 65.59 % )
        Info: Total interconnect delay = 1.698 ns ( 34.41 % )
Info: th for register "q_temp[7]" (data pin = "d[7]", clock pin = "g") is -1.596 ns
    Info: + Longest clock path from clock "g" to destination register is 2.879 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 2; CLK Node = 'g'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'g~clkctrl'
        Info: 3: + IC(1.444 ns) + CELL(0.206 ns) = 2.879 ns; Loc. = LCCOMB_X1_Y8_N20; Fanout = 1; REG Node = 'q_temp[7]'
        Info: Total cell delay = 1.296 ns ( 45.02 % )
        Info: Total interconnect delay = 1.583 ns ( 54.98 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 4.475 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_91; Fanout = 1; PIN Node = 'd[7]'
        Info: 2: + IC(2.759 ns) + CELL(0.616 ns) = 4.475 ns; Loc. = LCCOMB_X1_Y8_N20; Fanout = 1; REG Node = 'q_temp[7]'
        Info: Total cell delay = 1.716 ns ( 38.35 % )
        Info: Total interconnect delay = 2.759 ns ( 61.65 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings
    Info: Processing ended: Sat Mar 17 14:50:18 2007
    Info: Elapsed time: 00:00:02