cnt4_top.map.qmsg

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· QMSG 代码 · 共 14 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 18 22:38:04 2007 " "Info: Processing started: Fri May 18 22:38:04 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cnt4_top -c cnt4_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cnt4_top -c cnt4_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt4-one " "Info: Found design unit 1: cnt4-one" {  } { { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec/cnt4.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt4 " "Info: Found entity 1: cnt4" {  } { { "cnt4.vhd" "" { Text "D:/my_eda/cnt4_dec/cnt4.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcd_decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bcd_decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bcd_decoder-one " "Info: Found design unit 1: bcd_decoder-one" {  } { { "bcd_decoder.vhd" "" { Text "D:/my_eda/cnt4_dec/bcd_decoder.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bcd_decoder " "Info: Found entity 1: bcd_decoder" {  } { { "bcd_decoder.vhd" "" { Text "D:/my_eda/cnt4_dec/bcd_decoder.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt4_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file cnt4_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 cnt4_top " "Info: Found entity 1: cnt4_top" {  } { { "cnt4_top.bdf" "" { Schematic "D:/my_eda/cnt4_dec/cnt4_top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/my_eda/cnt4_dec/Vhdl1.vhd " "Warning: Can't analyze file -- file D:/my_eda/cnt4_dec/Vhdl1.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cnt4_top " "Info: Elaborating entity \"cnt4_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcd_decoder bcd_decoder:inst " "Info: Elaborating entity \"bcd_decoder\" for hierarchy \"bcd_decoder:inst\"" {  } { { "cnt4_top.bdf" "inst" { Schematic "D:/my_eda/cnt4_dec/cnt4_top.bdf" { { 128 384 496 224 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt4 cnt4:inst1 " "Info: Elaborating entity \"cnt4\" for hierarchy \"cnt4:inst1\"" {  } { { "cnt4_top.bdf" "inst1" { Schematic "D:/my_eda/cnt4_dec/cnt4_top.bdf" { { 128 232 328 224 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "y\[0\] GND " "Warning: Pin \"y\[0\]\" stuck at GND" {  } { { "cnt4_top.bdf" "" { Schematic "D:/my_eda/cnt4_dec/cnt4_top.bdf" { { 152 528 704 168 "y\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "31 " "Info: Implemented 31 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "20 " "Info: Implemented 20 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "142 " "Info: Allocated 142 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 18 22:38:17 2007 " "Info: Processing ended: Fri May 18 22:38:17 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}