d_reg.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity d_reg is
port(clk:in std_logic;----时钟
     din:in std_logic;----数据输入
     left_right:in std_logic;----方向控制信号
     dout_r:out std_logic;----右移输出
     dout_l:out std_logic);----左移输出
end;
architecture one of d_reg is
	signal q_temp:std_logic_vector(7 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
	if left_right='0' then q_temp(0)<=din;--左移
		q_temp(7 downto 1)<=q_temp(6 downto 0);
		--for i in 1 to 7 loop
		--q_temp(i)<=q_temp(i-1);
		--end loop; 
	else q_temp(7)<=din;--------------------右移
        q_temp(6 downto 0)<=q_temp(7 downto 1);
        --for i in 7 downto 1 loop
		--q_temp(i-1)<=q_temp(i);
		--end loop; 
	end if;
end if;
end process;
dout_r<=q_temp(0);
dout_l<=q_temp(7);
end;