lpm_fifo.map.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Mon Apr 23 16:19:19 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : lpm_fifo
Top-level Entity Name : lpm_fifo
Family : Stratix
Total logic elements : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge