clock_1.sim_ori.vwf

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· VWF 代码 · 共 2,420 行 · 第 1/3 页

VWF
2,420 行
字号
123
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 1.0us\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1";
	DATA_OFFSET = 0.0;
	DATA_DURATION = 300000.0;
	SIMULATION_TIME = 300000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clk1hz")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("clr")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("cnt")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("cnt[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "cnt";
}

SIGNAL("cnt[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "cnt";
}

SIGNAL("cnt[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "cnt";
}

SIGNAL("en")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("hour")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 5;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("hour[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "hour";
}

SIGNAL("hour[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "hour";
}

SIGNAL("hour[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "hour";
}

SIGNAL("hour[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "hour";
}

SIGNAL("hour[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "hour";
}

SIGNAL("min")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 6;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("min[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "min";
}

SIGNAL("min[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "min";
}

SIGNAL("min[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "min";
}

SIGNAL("min[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "min";
}

SIGNAL("min[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "min";
}

SIGNAL("min[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "min";
}

SIGNAL("sec")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 6;
	LSB_INDEX = 0;
	DIRECTION = REGISTERED;
	PARENT = "";
}

SIGNAL("sec[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "sec";
}

SIGNAL("sec[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "sec";
}

SIGNAL("sec[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "sec";
}

SIGNAL("sec[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "sec";
}

SIGNAL("sec[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "sec";
}

SIGNAL("sec[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = REGISTERED;
	PARENT = "sec";
}

SIGNAL("scan")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 6;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("scan[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "scan";
}

SIGNAL("scan[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "scan";
}

SIGNAL("scan[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "scan";
}

SIGNAL("scan[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "scan";
}

SIGNAL("scan[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "scan";
}

SIGNAL("scan[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "scan";
}

SIGNAL("seg")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 7;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("seg[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

SIGNAL("seg[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "seg";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 30000;
			LEVEL 0 FOR 5.0;
			LEVEL 1 FOR 5.0;
		}
	}
}

TRANSITION_LIST("clk1hz")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 4998.116;
		NODE
		{
			REPEAT = 29;
			LEVEL 1 FOR 5000.0;
			LEVEL 0 FOR 5000.0;
		}
		LEVEL 1 FOR 5000.0;
		LEVEL 0 FOR 1.884;
	}
}

TRANSITION_LIST("clr")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("cnt[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 38.123;
		NODE
		{
			REPEAT = 4999;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 40.0;
		}
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 1.877;
	}
}

TRANSITION_LIST("cnt[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 18.123;
		NODE
		{
			REPEAT = 4999;
			LEVEL 1 FOR 20.0;
			LEVEL 0 FOR 40.0;
		}
		LEVEL 1 FOR 20.0;
		LEVEL 0 FOR 21.877;
	}
}

TRANSITION_LIST("cnt[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 8.123;
		NODE
		{
			REPEAT = 14999;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 10.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 1.877;
	}
}

TRANSITION_LIST("en")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("hour[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("hour[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("hour[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("hour[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("hour[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("min[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("min[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("min[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("min[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("min[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("min[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("sec[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 300000.0;
	}
}

TRANSITION_LIST("sec[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 155001.513;
		LEVEL 1 FOR 144998.487;
	}
}

TRANSITION_LIST("sec[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 75001.513;
		LEVEL 1 FOR 80000.0;
		LEVEL 0 FOR 80000.0;
		LEVEL 1 FOR 64998.487;
	}
}

TRANSITION_LIST("sec[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 35001.513;
		NODE
		{
			REPEAT = 3;
			LEVEL 1 FOR 40000.0;
			LEVEL 0 FOR 40000.0;
		}
		LEVEL 1 FOR 24998.487;
	}
}

TRANSITION_LIST("sec[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 15001.513;
		NODE
		{
			REPEAT = 7;
			LEVEL 1 FOR 20000.0;
			LEVEL 0 FOR 20000.0;
		}
		LEVEL 1 FOR 4998.487;
	}
}

TRANSITION_LIST("sec[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 5001.513;
		NODE
		{
			REPEAT = 14;
			LEVEL 1 FOR 10000.0;
			LEVEL 0 FOR 10000.0;
		}
		LEVEL 1 FOR 10000.0;
		LEVEL 0 FOR 4998.487;
	}
}

TRANSITION_LIST("scan[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 44.309;
		NODE
		{
			REPEAT = 4999;
			LEVEL 1 FOR 0.17;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 9.83;
			LEVEL 0 FOR 40.0;
		}
		LEVEL 1 FOR 0.17;
		LEVEL 0 FOR 10.0;
		LEVEL 1 FOR 5.521;
	}
}

TRANSITION_LIST("scan[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 43.909;
		NODE
		{
			REPEAT = 4999;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 50.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 6.091;
	}
}

TRANSITION_LIST("scan[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 33.689;
		NODE
		{
			REPEAT = 4999;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 50.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 16.311;
	}
}
123

clock_1.sim_ori.vwf - 源码说明

本页面展示了「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）」中的 clock_1.sim_ori.vwf 源码文件，采用 VWF 编程语言编写，共 2,420 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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