decoder.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder is
port(clk20mhz:in std_logic;------系统时钟20mhz
     money_in:in integer range 0 to 8000;-------车费
     distance_in:in integer range 0 to 8000;----路程
     scan:out std_logic_vector(7 downto 0);-----7段显示控制信号(abcdefg)
     seg7:out std_logic_vector(6 downto 0);-----数码管地址选择信号
     dp:out std_logic);----------小数点
end;
architecture one of decoder is
     signal clk1khz:std_logic;----1khz的分频时钟，用于扫描数码管地址
     signal data:std_logic_vector(3 downto 0);
     signal m_one,m_ten,m_hun,m_tho:std_logic_vector(3 downto 0);---钱数的4位十进制表示
     signal d_one,d_ten,d_hun,d_tho:std_logic_vector(3 downto 0);---路程的4位十进制表示
begin
------------------------------------1khz分频,用于扫描数码管地址------
process(clk20mhz)
variable count:integer range 0 to 0;
begin
if clk20mhz'event and clk20mhz='1' then 
  if count=0 then clk1khz<=not clk1khz;count:=0;
  else count:=count+1;
  end if;
end if;
end process;
---------------------------------------计费的十进制转化为4位十进制数---
process(clk20mhz,money_in)
	variable comb1:integer range 0 to 8000;
	variable comb1_a,comb1_b,comb1_c,comb1_d:std_logic_vector(3 downto 0);
begin
if clk20mhz'event and clk20mhz='1' then
	if comb1<money_in then
		if comb1_a=9 and comb1_b=9 and comb1_c=9 then
			comb1_a:="0000";
			comb1_b:="0000";
			comb1_c:="0000";
			comb1_d:=comb1_d+1;
			comb1:=comb1+1;
		elsif comb1_a=9 and comb1_b=9 then
		    comb1_a:="0000";
			comb1_b:="0000";
			comb1_c:=comb1_c+1;
			comb1:=comb1+1;
		elsif comb1_a=9  then
		    comb1_a:="0000";
			comb1_b:=comb1_b+1;
			comb1:=comb1+1;
		else 
			comb1_a:=comb1_a+1;
			comb1:=comb1+1;
		end if;
	elsif comb1=money_in then
	    m_one<=comb1_a;
		m_ten<=comb1_b;
		m_hun<=comb1_c;
		m_tho<=comb1_d;
	elsif comb1>money_in then
		comb1_a:="0000";
		comb1_b:="0000";
		comb1_c:="0000";
		comb1_d:="0000";
		comb1:=0;
	end if;
end if;
end process;
------------------------------------路程的十进制转化为4位十进制数----
process(clk20mhz,distance_in)
	variable comb2:integer range 0 to 8000;
	variable comb2_a,comb2_b,comb2_c,comb2_d:std_logic_vector(3 downto 0);
begin
if clk20mhz'event and clk20mhz='1' then
	if comb2<distance_in then
		if comb2_a=9 and comb2_b=9 and comb2_c=9 then
			comb2_a:="0000";
			comb2_b:="0000";
			comb2_c:="0000";
			comb2_d:=comb2_d+1;
			comb2:=comb2+1;
		elsif comb2_a=9 and comb2_b=9 then
		    comb2_a:="0000";
			comb2_b:="0000";
			comb2_c:=comb2_c+1;
			comb2:=comb2+1;
		elsif comb2_a=9  then
		    comb2_a:="0000";
			comb2_b:=comb2_b+1;
			comb2:=comb2+1;
		else 
			comb2_a:=comb2_a+1;
			comb2:=comb2+1;
		end if;
	elsif comb2=distance_in then
	    d_one<=comb2_a;
		d_ten<=comb2_b;
		d_hun<=comb2_c;
		d_tho<=comb2_d;
	elsif comb2>distance_in then
		comb2_a:="0000";
		comb2_b:="0000";
		comb2_c:="0000";
		comb2_d:="0000";
		comb2:=0;
	end if;
end if;
end process;
-----------------------------------数码管动态扫描
process(clk1khz,m_one,m_ten,m_hun,m_tho,d_one,d_ten,d_hun,d_tho)
variable cnt:std_logic_vector(2 downto 0);
begin
if clk1khz'event and clk1khz='1' then
     cnt:=cnt+1;
end if;
case cnt is
	when"000"=>data<=m_one; dp<='0'; scan<="00000001";
	when"001"=>data<=m_ten; dp<='0'; scan<="00000010";
	when"010"=>data<=m_hun; dp<='1'; scan<="00000100";
	when"011"=>data<=m_tho; dp<='0'; scan<="00001000";
	when"100"=>data<=d_one; dp<='0'; scan<="00010000";
	when"101"=>data<=d_ten; dp<='0'; scan<="00100000";
	when"110"=>data<=d_hun; dp<='1'; scan<="01000000";
	when"111"=>data<=d_tho; dp<='0'; scan<="10000000";
end case;
end process;
-----------------------------------------七段译码--------------------
process(data)
begin
case data is
    when"0000"=>seg7<="1111110";
	when"0001"=>seg7<="0110000";
	when"0010"=>seg7<="1101101";
	when"0011"=>seg7<="1111001";
	when"0100"=>seg7<="0110011";
	when"0101"=>seg7<="1011011";
	when"0110"=>seg7<="1011111";
	when"0111"=>seg7<="1110000";
	when"1000"=>seg7<="1111111";
	when"1001"=>seg7<="1111011";
    when others=>seg7<="0000000";
end case;
end process;
end;