decoder.fit.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Thu Apr 19 15:40:32 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : decoder
Top-level Entity Name : decoder
Family : Cyclone II
Device : EP2C8T144C8
Timing Models : Final
Total logic elements : 219 / 8,256 ( 3 % )
    Total combinational functions : 203 / 8,256 ( 2 % )
    Dedicated logic registers : 94 / 8,256 ( 1 % )
Total registers : 94
Total pins : 43 / 85 ( 51 % )
Total virtual pins : 0
Total memory bits : 0 / 165,888 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )