lpm_rom.tan.rpt

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· RPT 代码 · 共 253 行 · 第 1/3 页

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                            ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                    ; To                                                                             ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[2] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[2] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[2] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[2] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[2] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[3] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[3] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[3] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[3] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[3] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[4] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[4] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[4] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[4] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[4] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[5] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[5] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[5] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[5] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[5] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[6] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[6] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[6] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[6] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[6] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[7] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[7] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[7] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[7] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[7] ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                                ;
+-------+--------------+------------+-----------+---------------------------------------------------------------------------------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From      ; To                                                                                                      ; To Clock ;
+-------+--------------+------------+-----------+---------------------------------------------------------------------------------------------------------+----------+
; N/A   ; None         ; 5.229 ns   ; adress[0] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg0 ; clk      ;
; N/A   ; None         ; 4.906 ns   ; adress[4] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg4 ; clk      ;
; N/A   ; None         ; 4.856 ns   ; adress[2] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg2 ; clk      ;
; N/A   ; None         ; 4.517 ns   ; adress[3] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; clk      ;
; N/A   ; None         ; 4.135 ns   ; adress[1] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; clk      ;
+-------+--------------+------------+-----------+---------------------------------------------------------------------------------------------------------+----------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                    ;
+-------+--------------+------------+--------------------------------------------------------------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                           ; To   ; From Clock ;
+-------+--------------+------------+--------------------------------------------------------------------------------+------+------------+
; N/A   ; None         ; 9.453 ns   ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[1] ; q[1] ; clk        ;
; N/A   ; None         ; 8.656 ns   ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[0] ; q[0] ; clk        ;
; N/A   ; None         ; 8.571 ns   ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[6] ; q[6] ; clk        ;
; N/A   ; None         ; 8.533 ns   ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[5] ; q[5] ; clk        ;
; N/A   ; None         ; 8.525 ns   ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[4] ; q[4] ; clk        ;
; N/A   ; None         ; 8.388 ns   ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[7] ; q[7] ; clk        ;
; N/A   ; None         ; 8.344 ns   ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[3] ; q[3] ; clk        ;
; N/A   ; None         ; 7.418 ns   ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|q_a[2] ; q[2] ; clk        ;
+-------+--------------+------------+--------------------------------------------------------------------------------+------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                       ;
+---------------+-------------+-----------+-----------+---------------------------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To                                                                                                      ; To Clock ;
+---------------+-------------+-----------+-----------+---------------------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; -3.822 ns ; adress[1] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg1 ; clk      ;
; N/A           ; None        ; -4.204 ns ; adress[3] ; rom:inst|altsyncram:altsyncram_component|altsyncram_h571:auto_generated|ram_block1a0~porta_address_reg3 ; clk      ;