sin.tan.rpt

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· RPT 代码 · 共 232 行 · 第 1/4 页

; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[4]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[5]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[6]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg1 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg2 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg3 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg4 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5 ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[7]                          ; clock      ; clock    ; None                        ; None                      ; 3.641 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[0]                                                                                             ; cnt:inst2|q1[5]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 2.358 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[0]                                                                                             ; cnt:inst2|q1[4]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 2.168 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[0]                                                                                             ; cnt:inst2|q1[3]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 2.082 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[1]                                                                                             ; cnt:inst2|q1[5]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 2.015 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[0]                                                                                             ; cnt:inst2|q1[2]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.996 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[2]                                                                                             ; cnt:inst2|q1[5]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.979 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[3]                                                                                             ; cnt:inst2|q1[5]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.893 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; cnt:inst2|q1[3]                                                                                             ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg3 ; clock      ; clock    ; None                        ; None                      ; 1.848 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[1]                                                                                             ; cnt:inst2|q1[4]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.825 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; cnt:inst2|q1[2]                                                                                             ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg2 ; clock      ; clock    ; None                        ; None                      ; 1.803 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[2]                                                                                             ; cnt:inst2|q1[4]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.789 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[4]                                                                                             ; cnt:inst2|q1[5]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.763 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[1]                                                                                             ; cnt:inst2|q1[3]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.739 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[2]                                                                                             ; cnt:inst2|q1[3]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.703 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[3]                                                                                             ; cnt:inst2|q1[4]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.703 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[1]                                                                                             ; cnt:inst2|q1[2]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.653 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[0]                                                                                             ; cnt:inst2|q1[1]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.519 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; cnt:inst2|q1[5]                                                                                             ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg5 ; clock      ; clock    ; None                        ; None                      ; 1.464 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; cnt:inst2|q1[4]                                                                                             ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg4 ; clock      ; clock    ; None                        ; None                      ; 1.462 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; cnt:inst2|q1[1]                                                                                             ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg1 ; clock      ; clock    ; None                        ; None                      ; 1.459 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[2]                                                                                             ; cnt:inst2|q1[2]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.223 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[3]                                                                                             ; cnt:inst2|q1[3]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.223 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[1]                                                                                             ; cnt:inst2|q1[1]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.175 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[4]                                                                                             ; cnt:inst2|q1[4]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.174 ns                ;
; N/A   ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; cnt:inst2|q1[0]                                                                                             ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|ram_block1a0~porta_address_reg0 ; clock      ; clock    ; None                        ; None                      ; 1.070 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[5]                                                                                             ; cnt:inst2|q1[5]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 1.043 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; cnt:inst2|q1[0]                                                                                             ; cnt:inst2|q1[0]                                                                                             ; clock      ; clock    ; None                        ; None                      ; 0.501 ns                ;
+-------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                        ;
+-------+--------------+------------+------------------------------------------------------------------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                               ; To   ; From Clock ;
+-------+--------------+------------+------------------------------------------------------------------------------------+------+------------+
; N/A   ; None         ; 9.061 ns   ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[3] ; q[3] ; clock      ;
; N/A   ; None         ; 8.125 ns   ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[2] ; q[2] ; clock      ;
; N/A   ; None         ; 8.111 ns   ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[4] ; q[4] ; clock      ;
; N/A   ; None         ; 8.075 ns   ; sin_rom:inst|altsyncram:altsyncram_component|altsyncram_4871:auto_generated|q_a[5] ; q[5] ; clock      ;