dds_acc.h
来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· C头文件 代码 · 共 911 行 · 第 1/4 页
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911 行
* '<Root>/Input1'
*/
real_T Input1_P1; /* Expression: -1
* '<Root>/Input1'
*/
real_T Input1_P2_Size[2]; /* Computed Parameter: P2Size
* '<Root>/Input1'
*/
real_T Input1_P2; /* Expression: bwl
* '<Root>/Input1'
*/
real_T Input1_P3_Size[2]; /* Computed Parameter: P3Size
* '<Root>/Input1'
*/
real_T Input1_P3; /* Expression: bwr
* '<Root>/Input1'
*/
real_T Input1_P4_Size[2]; /* Computed Parameter: P4Size
* '<Root>/Input1'
*/
real_T Input1_P4[58]; /* Expression: ppat
* '<Root>/Input1'
*/
real_T Input1_P5_Size[2]; /* Computed Parameter: P5Size
* '<Root>/Input1'
*/
real_T Input1_P5; /* Expression: 0
* '<Root>/Input1'
*/
real_T Input1_P6_Size[2]; /* Computed Parameter: P6Size
* '<Root>/Input1'
*/
real_T Input1_P6; /* Expression: 0
* '<Root>/Input1'
*/
real_T Input1_P7_Size[2]; /* Computed Parameter: P7Size
* '<Root>/Input1'
*/
real_T Input1_P7; /* Expression: bp
* '<Root>/Input1'
*/
real_T Input1_P8_Size[2]; /* Computed Parameter: P8Size
* '<Root>/Input1'
*/
real_T Input1_P8; /* Expression: 1
* '<Root>/Input1'
*/
real_T Input1_P9_Size[2]; /* Computed Parameter: P9Size
* '<Root>/Input1'
*/
real_T Input1_P9; /* Expression: 0
* '<Root>/Input1'
*/
real_T Input1_P10_Size[2]; /* Computed Parameter: P10Size
* '<Root>/Input1'
*/
real_T Input1_P10; /* Expression: 0
* '<Root>/Input1'
*/
real_T Input1_P11_Size[2]; /* Computed Parameter: P11Size
* '<Root>/Input1'
*/
real_T Input1_P11[6]; /* Expression: modulename
* '<Root>/Input1'
*/
real_T Input1_P12_Size[2]; /* Computed Parameter: P12Size
* '<Root>/Input1'
*/
real_T Input1_P12; /* Expression: nSgCpl
* '<Root>/Input1'
*/
real_T Input1_P13_Size[2]; /* Computed Parameter: P13Size
* '<Root>/Input1'
*/
real_T Input1_P13; /* Expression: sgn
* '<Root>/Input1'
*/
real_T Input2_P1_Size[2]; /* Computed Parameter: P1Size
* '<Root>/Input2'
*/
real_T Input2_P1; /* Expression: -1
* '<Root>/Input2'
*/
real_T Input2_P2_Size[2]; /* Computed Parameter: P2Size
* '<Root>/Input2'
*/
real_T Input2_P2; /* Expression: bwl
* '<Root>/Input2'
*/
real_T Input2_P3_Size[2]; /* Computed Parameter: P3Size
* '<Root>/Input2'
*/
real_T Input2_P3; /* Expression: bwr
* '<Root>/Input2'
*/
real_T Input2_P4_Size[2]; /* Computed Parameter: P4Size
* '<Root>/Input2'
*/
real_T Input2_P4[58]; /* Expression: ppat
* '<Root>/Input2'
*/
real_T Input2_P5_Size[2]; /* Computed Parameter: P5Size
* '<Root>/Input2'
*/
real_T Input2_P5; /* Expression: 0
* '<Root>/Input2'
*/
real_T Input2_P6_Size[2]; /* Computed Parameter: P6Size
* '<Root>/Input2'
*/
real_T Input2_P6; /* Expression: 0
* '<Root>/Input2'
*/
real_T Input2_P7_Size[2]; /* Computed Parameter: P7Size
* '<Root>/Input2'
*/
real_T Input2_P7; /* Expression: bp
* '<Root>/Input2'
*/
real_T Input2_P8_Size[2]; /* Computed Parameter: P8Size
* '<Root>/Input2'
*/
real_T Input2_P8; /* Expression: 1
* '<Root>/Input2'
*/
real_T Input2_P9_Size[2]; /* Computed Parameter: P9Size
* '<Root>/Input2'
*/
real_T Input2_P9; /* Expression: 0
* '<Root>/Input2'
*/
real_T Input2_P10_Size[2]; /* Computed Parameter: P10Size
* '<Root>/Input2'
*/
real_T Input2_P10; /* Expression: 0
* '<Root>/Input2'
*/
real_T Input2_P11_Size[2]; /* Computed Parameter: P11Size
* '<Root>/Input2'
*/
real_T Input2_P11[6]; /* Expression: modulename
* '<Root>/Input2'
*/
real_T Input2_P12_Size[2]; /* Computed Parameter: P12Size
* '<Root>/Input2'
*/
real_T Input2_P12; /* Expression: nSgCpl
* '<Root>/Input2'
*/
real_T Input2_P13_Size[2]; /* Computed Parameter: P13Size
* '<Root>/Input2'
*/
real_T Input2_P13; /* Expression: sgn
* '<Root>/Input2'
*/
real_T LUT_P1_Size[2]; /* Computed Parameter: P1Size
* '<Root>/LUT'
*/
real_T LUT_P1; /* Expression: -1
* '<Root>/LUT'
*/
real_T LUT_P2_Size[2]; /* Computed Parameter: P2Size
* '<Root>/LUT'
*/
real_T LUT_P2; /* Expression: bwl
* '<Root>/LUT'
*/
real_T LUT_P3_Size[2]; /* Computed Parameter: P3Size
* '<Root>/LUT'
*/
real_T LUT_P3; /* Expression: bwr
* '<Root>/LUT'
*/
real_T LUT_P4_Size[2]; /* Computed Parameter: P4Size
* '<Root>/LUT'
*/
real_T LUT_P4; /* Expression: bwaddr
* '<Root>/LUT'
*/
real_T LUT_P5_Size[2]; /* Computed Parameter: P5Size
* '<Root>/LUT'
*/
real_T LUT_P5[1025]; /* Expression: MatlabArray
* '<Root>/LUT'
*/
real_T LUT_P6_Size[2]; /* Computed Parameter: P6Size
* '<Root>/LUT'
*/
real_T LUT_P6[40]; /* Expression: modulename
* '<Root>/LUT'
*/
real_T LUT_P7_Size[2]; /* Computed Parameter: P7Size
* '<Root>/LUT'
*/
real_T LUT_P7; /* Expression: BusType
* '<Root>/LUT'
*/
real_T LUT_P8_Size[2]; /* Computed Parameter: P8Size
* '<Root>/LUT'
*/
real_T LUT_P8; /* Expression: IslibDir
* '<Root>/LUT'
*/
real_T LUT_P9_Size[2]; /* Computed Parameter: P9Size
* '<Root>/LUT'
*/
real_T LUT_P9; /* Expression: pipeline
* '<Root>/LUT'
*/
real_T LUT_P10_Size[2]; /* Computed Parameter: P10Size
* '<Root>/LUT'
*/
real_T LUT_P10; /* Expression: clken
* '<Root>/LUT'
*/
real_T LUT_P11_Size[2]; /* Computed Parameter: P11Size
* '<Root>/LUT'
*/
real_T LUT_P11; /* Expression: ena
* '<Root>/LUT'
*/
};
extern Parameters_dds dds_DefaultParameters; /* parameters */
#endif /* _RTW_HEADER_dds_acc_h_ */
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