hyperthermia_top.fit.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Fitter report for Hyperthermia_top
Tue May 29 20:13:27 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. Bidir Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Delay Chain Summary
 14. Pad To Core Delay Chain Fanout
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Fitter RAM Summary
 19. Interconnect Usage Summary
 20. LAB Logic Elements
 21. LAB-wide Signals
 22. LAB Signals Sourced
 23. LAB Signals Sourced Out
 24. LAB Distinct Inputs
 25. Fitter Device Options
 26. Advanced Data - General
 27. Advanced Data - Placement Preparation
 28. Advanced Data - Placement
 29. Advanced Data - Routing
 30. Fitter Messages
 31. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Fitter Summary                                                               ;
+------------------------------------+-----------------------------------------+
; Fitter Status                      ; Successful - Tue May 29 20:13:27 2007   ;
; Quartus II Version                 ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name                      ; Hyperthermia_top                        ;
; Top-level Entity Name              ; Hyperthermia_top                        ;
; Family                             ; Cyclone II                              ;
; Device                             ; EP2C8T144C8                             ;
; Timing Models                      ; Final                                   ;
; Total logic elements               ; 411 / 8,256 ( 5 % )                     ;
;     Total combinational functions  ; 405 / 8,256 ( 5 % )                     ;
;     Dedicated logic registers      ; 91 / 8,256 ( 1 % )                      ;
; Total registers                    ; 91                                      ;
; Total pins                         ; 38 / 85 ( 45 % )                        ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 1,024 / 165,888 ( < 1 % )               ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % )                          ;
; Total PLLs                         ; 0 / 2 ( 0 % )                           ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                          ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                 ; Setting                        ; Default Value                  ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                 ; EP2C8T144C8                    ;                                ;
; Fit Attempts to Skip                                   ; 0                              ; 0.0                            ;
; Always Enable Input Buffers                            ; Off                            ; Off                            ;
; Router Timing Optimization Level                       ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                            ; 1.0                            ; 1.0                            ;