📄 hyperthermia_top.map.rpt
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+--------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+--------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------------------+
; sepcified_temp_top:inst2|specified_temp:inst|temp[0] ; set ; yes ;
; sepcified_temp_top:inst2|specified_temp:inst|temp[2] ; set ; yes ;
; sepcified_temp_top:inst2|specified_temp:inst|temp[1] ; set ; yes ;
; sepcified_temp_top:inst2|specified_temp:inst|temp[3] ; set ; yes ;
; display:inst4|two_to_ten:inst|inte_one[0] ; display:inst4|two_to_ten:inst|comb~185 ; yes ;
; display:inst4|two_to_ten:inst|inte_one[1] ; display:inst4|two_to_ten:inst|comb~185 ; yes ;
; display:inst4|two_to_ten:inst|inte_one[2] ; display:inst4|two_to_ten:inst|comb~185 ; yes ;
; display:inst4|two_to_ten:inst|inte_one[3] ; display:inst4|two_to_ten:inst|comb~185 ; yes ;
; sepcified_temp_top:inst2|specified_temp:inst|temp[9] ; set ; yes ;
; sepcified_temp_top:inst2|specified_temp:inst|temp[8] ; set ; yes ;
; sepcified_temp_top:inst2|specified_temp:inst|temp[7] ; set ; yes ;
; sepcified_temp_top:inst2|specified_temp:inst|temp[6] ; set ; yes ;
; sepcified_temp_top:inst2|specified_temp:inst|temp[5] ; set ; yes ;
; sepcified_temp_top:inst2|specified_temp:inst|temp[4] ; set ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[0] ; two_dimension_top:inst1|two_dimension_fuzzy:inst|comb~20 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[1] ; two_dimension_top:inst1|two_dimension_fuzzy:inst|comb~20 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|rt[2] ; two_dimension_top:inst1|two_dimension_fuzzy:inst|comb~20 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|e[0] ; GND ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|e[1] ; GND ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|e[2] ; GND ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|e[3] ; GND ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[9] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[8] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[7] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[6] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[5] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[4] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[3] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[2] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[1] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; two_dimension_top:inst1|two_dimension_fuzzy:inst|t_rate_n[0] ; two_dimension_top:inst1|add_sub:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_ijf:auto_generated|op_1 ; yes ;
; Number of user-specified and inferred latches = 31 ; ; ;
+--------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+--------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+--------------------------------+
; inst/\process4:count[0] ; Merged with inst1/inst6/cnt[0] ;
; inst1/inst11/count[0] ; Merged with inst1/inst6/cnt[0] ;
; inst1/inst11/count[1] ; Merged with inst1/inst6/cnt[1] ;
; Total Number of Removed Registers = 3 ; ;
+---------------------------------------+--------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |Hyperthermia_top|sepcified_temp_top:inst2|specified_temp:inst|num_rise[1] ;
; 7:1 ; 2 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |Hyperthermia_top|two_dimension_top:inst1|two_dimension_fuzzy:inst|comb~27 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component|altsyncram_p971:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+----------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+----------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: two_dimension_top:inst1|lpm_rom0:inst5|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+---------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------------+---------------------------------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 4 ; Signed Integer ;
; WIDTHAD_A ; 8 ; Signed Integer ;
; NUMWORDS_A ; 256 ; Signed Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; rom_data.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
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