hyperthermia_top.fit.summary

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

Fitter Status : Successful - Tue May 29 20:13:27 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : Hyperthermia_top
Top-level Entity Name : Hyperthermia_top
Family : Cyclone II
Device : EP2C8T144C8
Timing Models : Final
Total logic elements : 411 / 8,256 ( 5 % )
    Total combinational functions : 405 / 8,256 ( 5 % )
    Dedicated logic registers : 91 / 8,256 ( 1 % )
Total registers : 91
Total pins : 38 / 85 ( 45 % )
Total virtual pins : 0
Total memory bits : 1,024 / 165,888 ( < 1 % )
Embedded Multiplier 9-bit elements : 0 / 36 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )