📄 shift.v
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`timescale 1ns/10ps
module shift(
//input
clk,
rst,
s,
in,
//output
out);
input clk,rst;
input [3:0]s;
input [7:0]in;
output [7:0]out;
reg [7:0]vol;
assign out=vol;
always @(posedge clk)
begin
if (!rst)
vol<=8'h0;
else
begin
if(s==4'h0)
vol<=vol;
else if (s==4'h1)
vol<={in[6:0],1'b0};
else if (s==4'h2)
vol<={in[5:0],2'b0};
else if (s==4'h3)
vol<={in[4:0],3'b0};
else if (s==4'h4)
vol<={in[3:0],4'b0};
else if (s==4'h5)
vol<={in[2:0],5'b0};
else if (s==4'h6)
vol<={in[1:0],6'b0};
else if (s==4'h7)
vol<={in[0],7'b0};
else if (s==4'h8)
vol<=in;
else if (s==4'hf)
vol<={1'b0,in[7:1]};
else if (s==4'he)
vol<={2'b0,in[7:2]};
else if (s==4'hd)
vol<={3'b0,in[7:3]};
else if (s==4'hc)
vol<={4'b0,in[7:4]};
else if (s==4'hb)
vol<={5'b0,in[7:5]};
else if (s==4'ha)
vol<={6'b0,in[7:6]};
else // (s==4'h9)
vol<={7'b0,in[7]};
end
end
always @(negedge rst)
begin
vol<=8'h0;
end
endmodule
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