de2_lcm_test.tan.summary

基於DE2系統的LCM verilog code,在LCM右下方顯示數字,每按一次按鍵數字會加1,顏色也會改變

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.491 ns
From           : KEY[0]
To             : I2S_LCM_Config:u4|mI2S_DATA[12]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 37.553 ns
From           : H_Cont[3]
To             : GPIO_0[25]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.321 ns
From           : KEY[0]
To             : TD_RESET
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.261 ns
From           : KEY[0]
To             : I2S_LCM_Config:u4|mI2S_DATA[12]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : 7.797 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 226.96 MHz ( period = 4.406 ns )
From           : I2S_LCM_Config:u4|mI2S_STR
To             : I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA~en
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
Slack          : 49.825 ns
Required Time  : 18.42 MHz ( period = 54.285 ns )
Actual Time    : 224.22 MHz ( period = 4.460 ns )
From           : H_Cont[5]
To             : V_Cont[0]
From Clock     : LCM_PLL:u0|altpll:altpll_component|_clk0
To Clock       : LCM_PLL:u0|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'KEY[1]'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 450.05 MHz ( period = 2.222 ns )
From           : color[1]
To             : color[2]
From Clock     : KEY[1]
To Clock       : KEY[1]
Failed Paths   : 0

Type           : Clock Hold: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
Slack          : 0.391 ns
Required Time  : 18.42 MHz ( period = 54.285 ns )
Actual Time    : N/A
From           : oVGA_V_SYNC
To             : oVGA_V_SYNC
From Clock     : LCM_PLL:u0|altpll:altpll_component|_clk0
To Clock       : LCM_PLL:u0|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.391 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : I2S_LCM_Config:u4|LUT_INDEX[0]
To             : I2S_LCM_Config:u4|LUT_INDEX[0]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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