counter.vhd

来自「此程序为脉宽测量电路vhdl代码」· VHDL 代码 · 共 45 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity counter is
port(
	clk: in std_logic;
	clk10: in std_logic;
	s_state: in std_logic_vector (1 downto 0);
	data: inout std_logic_vector (7 downto 0);
	s_fout: out std_logic
	);
end counter;

architecture behaver of counter is
	signal tempdata: std_logic_vector (7 downto 0);
begin
	process (clk,clk10,s_state)
	begin
		if clk'event and clk='1' then
			case s_state is
				when "00" => 
					data<="00000000";
					s_fout<='0';
				when "01" =>
					if clk10'event and clk10='1' then
						if data<"11111111" then
							data<=data+'1';
						else
							data<="11111111";
							s_fout<='1';
						end if;
					end if;
					tempdata<=data;
				when "11" =>
					data<=tempdata;
				when others =>
					data<="00000000";
					s_fout<='0';
			end case;
		end if;
	end process;
end behaver;