d02.vhd

来自「此程序为脉宽测量电路vhdl代码」· VHDL 代码 · 共 54 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity d02 is
port(
	clk,clk10: in std_logic;
	pulse,reset: in std_logic;
	sel: out std_logic_vector (5 downto 0);		-- select signal
	leds: out std_logic_vector (7 downto 0);	-- 8_leds
	fout: out std_logic
	);
end d02;

architecture behaver of d02 is
	component display is		-- submodule of display
	port(
		clk: in std_logic;
		data: in std_logic_vector (7 downto 0);
		s_fout: in std_logic;
		sel: out std_logic_vector (5 downto 0);
		leds: out std_logic_vector (7 downto 0);
		fout: out std_logic
		);
	end component;
	component counter is		-- submodule of counter
	port(
		clk: in std_logic;
		clk10: in std_logic;
		s_state: in std_logic_vector (1 downto 0);
		data: inout std_logic_vector (7 downto 0);
		s_fout: out std_logic
		);
	end component;
	component control is		-- submodule os control
	port(
		clk: in std_logic;
		reset: in std_logic;
		pulse: in std_logic;
		s_state: out std_logic_vector (1 downto 0)
		);
	end component;
	
	signal data: std_logic_vector (7 downto 0);
	signal s_fout: std_logic;
	signal s_state: std_logic_vector (1 downto 0);
	
begin
	u0: display port map (clk,data,s_fout,sel,leds,fout);
	u1: counter port map (clk,clk10,s_state,data,s_fout);
	u2: control port map (clk,reset,pulse,s_state);
end behaver;