📄 taxi.sim.rpt
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; Missing 1-Value Coverage ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; |taxi|mm[10] ; |taxi|mm[10] ; data_out0 ;
; |taxi|mm[11] ; |taxi|mm[11] ; data_out0 ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] ; cout ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[7] ; cout ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] ; cout ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[8] ; cout ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] ; cout ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[9] ; cout ;
; |taxi|lpm_add_sub:Add2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |taxi|lpm_add_sub:Add2|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; data_out0 ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] ; cout ;
; |taxi|mm~961 ; |taxi|mm~961 ; data_out0 ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; data_out0 ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[10] ; cout ;
; |taxi|mm~962 ; |taxi|mm~962 ; data_out0 ;
; |taxi|mm~964 ; |taxi|mm~964 ; data_out0 ;
; |taxi|lpm_add_sub:Add2|addcore:adder|unreg_res_node[6] ; |taxi|lpm_add_sub:Add2|addcore:adder|unreg_res_node[6] ; data_out0 ;
; |taxi|lpm_add_sub:Add0|addcore:adder|unreg_res_node[11] ; |taxi|lpm_add_sub:Add0|addcore:adder|unreg_res_node[11] ; data_out0 ;
; |taxi|lpm_add_sub:Add1|addcore:adder|unreg_res_node[11] ; |taxi|lpm_add_sub:Add1|addcore:adder|unreg_res_node[11] ; data_out0 ;
; |taxi|reset ; |taxi|reset ; dataout ;
; |taxi|count3[2] ; |taxi|count3[2] ; padio ;
; |taxi|count3[3] ; |taxi|count3[3] ; padio ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; |taxi|mm[9] ; |taxi|mm[9] ; data_out0 ;
; |taxi|mm[10] ; |taxi|mm[10] ; data_out0 ;
; |taxi|mm[11] ; |taxi|mm[11] ; data_out0 ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] ; cout ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[7] ; cout ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] ; cout ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[8] ; cout ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ; data_out0 ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[9] ; cout ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ; data_out0 ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[9] ; cout ;
; |taxi|lpm_add_sub:Add2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |taxi|lpm_add_sub:Add2|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; data_out0 ;
; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; |taxi|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[10] ; cout ;
; |taxi|mm~961 ; |taxi|mm~961 ; data_out0 ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; data_out0 ;
; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] ; |taxi|lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[10] ; cout ;
; |taxi|mm~962 ; |taxi|mm~962 ; data_out0 ;
; |taxi|mm~964 ; |taxi|mm~964 ; data_out0 ;
; |taxi|lpm_add_sub:Add2|addcore:adder|unreg_res_node[6] ; |taxi|lpm_add_sub:Add2|addcore:adder|unreg_res_node[6] ; data_out0 ;
; |taxi|lpm_add_sub:Add0|addcore:adder|unreg_res_node[11] ; |taxi|lpm_add_sub:Add0|addcore:adder|unreg_res_node[11] ; data_out0 ;
; |taxi|lpm_add_sub:Add1|addcore:adder|unreg_res_node[11] ; |taxi|lpm_add_sub:Add1|addcore:adder|unreg_res_node[11] ; data_out0 ;
; |taxi|reset ; |taxi|reset ; dataout ;
; |taxi|count3[1] ; |taxi|count3[1] ; padio ;
; |taxi|count3[2] ; |taxi|count3[2] ; padio ;
; |taxi|count3[3] ; |taxi|count3[3] ; padio ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
Info: Processing started: Thu May 31 11:59:43 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off taxi -c taxi
Info: Using vector source file "D:/pro1/taxiclk.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 72.92 %
Info: Number of transitions in simulation is 6278
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Allocated 86 megabytes of memory during processing
Info: Processing ended: Thu May 31 11:59:44 2007
Info: Elapsed time: 00:00:01
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