📄 taxi.tan.rpt
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; N/A ; 45.87 MHz ( period = 21.800 ns ) ; mm[7] ; mm[9] ; clk ; clk ; None ; None ; 18.200 ns ;
; N/A ; 45.87 MHz ( period = 21.800 ns ) ; mm[8] ; mm[11] ; clk ; clk ; None ; None ; 18.200 ns ;
; N/A ; 46.08 MHz ( period = 21.700 ns ) ; mm[6] ; mm[8] ; clk ; clk ; None ; None ; 18.100 ns ;
; N/A ; 46.08 MHz ( period = 21.700 ns ) ; mm[9] ; mm[11] ; clk ; clk ; None ; None ; 18.100 ns ;
; N/A ; 46.30 MHz ( period = 21.600 ns ) ; mm[7] ; mm[8] ; clk ; clk ; None ; None ; 18.000 ns ;
; N/A ; 46.51 MHz ( period = 21.500 ns ) ; mm[8] ; mm[10] ; clk ; clk ; None ; None ; 17.900 ns ;
; N/A ; 46.73 MHz ( period = 21.400 ns ) ; mm[9] ; mm[10] ; clk ; clk ; None ; None ; 17.800 ns ;
; N/A ; 46.95 MHz ( period = 21.300 ns ) ; mm[8] ; mm[9] ; clk ; clk ; None ; None ; 17.700 ns ;
; N/A ; 47.17 MHz ( period = 21.200 ns ) ; mm[9] ; mm[9] ; clk ; clk ; None ; None ; 17.600 ns ;
; N/A ; 48.78 MHz ( period = 20.500 ns ) ; mm[10] ; mm[11] ; clk ; clk ; None ; None ; 16.900 ns ;
; N/A ; 49.26 MHz ( period = 20.300 ns ) ; mm[10] ; mm[10] ; clk ; clk ; None ; None ; 16.700 ns ;
; N/A ; 50.76 MHz ( period = 19.700 ns ) ; mm[8] ; mm[8] ; clk ; clk ; None ; None ; 16.100 ns ;
; N/A ; 60.24 MHz ( period = 16.600 ns ) ; mm[11] ; mm[11] ; clk ; clk ; None ; None ; 13.000 ns ;
; N/A ; 68.03 MHz ( period = 14.700 ns ) ; mm[0] ; mm[6] ; clk ; clk ; None ; None ; 11.100 ns ;
; N/A ; 68.97 MHz ( period = 14.500 ns ) ; mm[2] ; mm[6] ; clk ; clk ; None ; None ; 10.900 ns ;
; N/A ; 69.44 MHz ( period = 14.400 ns ) ; mm[1] ; mm[6] ; clk ; clk ; None ; None ; 10.800 ns ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; mm[4] ; mm[6] ; clk ; clk ; None ; None ; 10.300 ns ;
; N/A ; 71.94 MHz ( period = 13.900 ns ) ; mm[5] ; mm[6] ; clk ; clk ; None ; None ; 10.300 ns ;
; N/A ; 72.46 MHz ( period = 13.800 ns ) ; mm[3] ; mm[6] ; clk ; clk ; None ; None ; 10.200 ns ;
; N/A ; 73.53 MHz ( period = 13.600 ns ) ; mm[0] ; mm[4] ; clk ; clk ; None ; None ; 10.000 ns ;
; N/A ; 75.19 MHz ( period = 13.300 ns ) ; mm[1] ; mm[4] ; clk ; clk ; None ; None ; 9.700 ns ;
; N/A ; 78.74 MHz ( period = 12.700 ns ) ; mm[2] ; mm[4] ; clk ; clk ; None ; None ; 9.100 ns ;
; N/A ; 78.74 MHz ( period = 12.700 ns ) ; mm[3] ; mm[4] ; clk ; clk ; None ; None ; 9.100 ns ;
; N/A ; 79.37 MHz ( period = 12.600 ns ) ; mm[4] ; mm[4] ; clk ; clk ; None ; None ; 9.000 ns ;
; N/A ; 80.00 MHz ( period = 12.500 ns ) ; mm[6] ; mm[6] ; clk ; clk ; None ; None ; 8.900 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; mm[0] ; mm[1] ; clk ; clk ; None ; None ; 8.700 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; mm[1] ; mm[1] ; clk ; clk ; None ; None ; 8.700 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; mm[3] ; mm[1] ; clk ; clk ; None ; None ; 8.700 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; mm[0] ; mm[3] ; clk ; clk ; None ; None ; 8.700 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; mm[1] ; mm[3] ; clk ; clk ; None ; None ; 8.700 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; mm[3] ; mm[3] ; clk ; clk ; None ; None ; 8.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; mm[2] ; mm[1] ; clk ; clk ; None ; None ; 8.200 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; mm[2] ; mm[3] ; clk ; clk ; None ; None ; 8.200 ns ;
; N/A ; 85.47 MHz ( period = 11.700 ns ) ; mm[2] ; mm[2] ; clk ; clk ; None ; None ; 8.100 ns ;
; N/A ; 96.15 MHz ( period = 10.400 ns ) ; mm[0] ; mm[2] ; clk ; clk ; None ; None ; 6.800 ns ;
; N/A ; 99.01 MHz ( period = 10.100 ns ) ; mm[1] ; mm[2] ; clk ; clk ; None ; None ; 6.500 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; mm[0] ; mm[0] ; clk ; clk ; None ; None ; 2.300 ns ;
+-------+------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+-----------+------------+
; N/A ; None ; 18.400 ns ; mm[7] ; en1 ; clk ;
; N/A ; None ; 18.300 ns ; mm[8] ; en1 ; clk ;
; N/A ; None ; 18.300 ns ; mm[9] ; en1 ; clk ;
; N/A ; None ; 17.700 ns ; mm[5] ; en1 ; clk ;
; N/A ; None ; 17.400 ns ; mm[4] ; en1 ; clk ;
; N/A ; None ; 15.900 ns ; mm[6] ; en1 ; clk ;
; N/A ; None ; 15.500 ns ; mm[11] ; en1 ; clk ;
; N/A ; None ; 15.000 ns ; mm[10] ; en1 ; clk ;
; N/A ; None ; 14.300 ns ; mm[11] ; count3[3] ; clk ;
; N/A ; None ; 14.300 ns ; mm[10] ; count3[2] ; clk ;
; N/A ; None ; 14.100 ns ; mm[8] ; count3[0] ; clk ;
; N/A ; None ; 14.000 ns ; mm[6] ; count2[2] ; clk ;
; N/A ; None ; 13.900 ns ; mm[1] ; count1[1] ; clk ;
; N/A ; None ; 13.500 ns ; mm[9] ; count3[1] ; clk ;
; N/A ; None ; 13.500 ns ; mm[7] ; count2[3] ; clk ;
; N/A ; None ; 13.400 ns ; mm[4] ; count2[0] ; clk ;
; N/A ; None ; 13.200 ns ; mm[0] ; count1[0] ; clk ;
; N/A ; None ; 12.600 ns ; mm[5] ; count2[1] ; clk ;
; N/A ; None ; 12.400 ns ; mm[3] ; count1[3] ; clk ;
; N/A ; None ; 12.400 ns ; mm[2] ; count1[2] ; clk ;
+-------+--------------+------------+--------+-----------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
Info: Processing started: Thu May 31 11:58:48 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off taxi -c taxi
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 38.31 MHz between source register "mm[0]" and destination register "mm[10]" (period= 26.1 ns)
Info: + Longest register to register delay is 22.500 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C17; Fanout = 5; REG Node = 'mm[0]'
Info: 2: + IC(2.300 ns) + CELL(1.200 ns) = 3.500 ns; Loc. = LC3_C13; Fanout = 1; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]'
Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.800 ns; Loc. = LC4_C13; Fanout = 1; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]'
Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC5_C13; Fanout = 1; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2]'
Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.400 ns; Loc. = LC6_C13; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3]'
Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.700 ns; Loc. = LC7_C13; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4]'
Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 5.000 ns; Loc. = LC8_C13; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5]'
Info: 8: + IC(0.800 ns) + CELL(0.300 ns) = 6.100 ns; Loc. = LC1_C15; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6]'
Info: 9: + IC(0.000 ns) + CELL(1.300 ns) = 7.400 ns; Loc. = LC2_C15; Fanout = 2; COMB Node = 'lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]'
Info: 10: + IC(2.200 ns) + CELL(1.800 ns) = 11.400 ns; Loc. = LC2_C16; Fanout = 2; COMB Node = 'mm~948'
Info: 11: + IC(0.600 ns) + CELL(2.300 ns) = 14.300 ns; Loc. = LC1_C16; Fanout = 1; COMB Node = 'Equal1~55'
Info: 12: + IC(2.200 ns) + CELL(2.300 ns) = 18.800 ns; Loc. = LC2_C18; Fanout = 6; COMB Node = 'Equal1~56'
Info: 13: + IC(2.500 ns) + CELL(1.200 ns) = 22.500 ns; Loc. = LC3_C23; Fanout = 6; REG Node = 'mm[10]'
Info: Total cell delay = 11.900 ns ( 52.89 % )
Info: Total interconnect delay = 10.600 ns ( 47.11 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 5.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'clk'
Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C23; Fanout = 6; REG Node = 'mm[10]'
Info: Total cell delay = 2.800 ns ( 52.83 % )
Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: - Longest clock path from clock "clk" to source register is 5.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'clk'
Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C17; Fanout = 5; REG Node = 'mm[0]'
Info: Total cell delay = 2.800 ns ( 52.83 % )
Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Micro setup delay of destination is 2.500 ns
Info: tco from clock "clk" to destination pin "en1" through register "mm[7]" is 18.400 ns
Info: + Longest clock path from clock "clk" to source register is 5.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 12; CLK Node = 'clk'
Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_C16; Fanout = 6; REG Node = 'mm[7]'
Info: Total cell delay = 2.800 ns ( 52.83 % )
Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Longest register to pin delay is 12.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C16; Fanout = 6; REG Node = 'mm[7]'
Info: 2: + IC(2.600 ns) + CELL(1.700 ns) = 4.300 ns; Loc. = LC1_C23; Fanout = 1; COMB Node = 'LessThan0~78'
Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.800 ns; Loc. = LC2_C23; Fanout = 1; COMB Node = 'LessThan0~75'
Info: 4: + IC(1.100 ns) + CELL(5.100 ns) = 12.000 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'en1'
Info: Total cell delay = 8.300 ns ( 69.17 % )
Info: Total interconnect delay = 3.700 ns ( 30.83 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 98 megabytes of memory during processing
Info: Processing ended: Thu May 31 11:58:48 2007
Info: Elapsed time: 00:00:00
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