top.vt

Altera基本宏功能应用设计实例 &#61548 “Example-b4-1Project”目录下为设计工程 &#61548 “Example-b4-1Solution”目录下为正确的解决方

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors  
// are exported from a vector file in the Quartus Waveform Editor and apply to  
// the top level entity of the current Quartus project .The user can use this   
// testbench to simulate his design using a third-party simulation tool .       
// *****************************************************************************
// Generated on "10/24/2004 23:43:18"
                                                                        
// Verilog Self-Checking Test Bench (with test vectors) for design :    TOP
// 
// Simulation tool : 3rd Party
// 

`timescale 1 ps/ 1 ps
module TOP_vlg_vec_tst();
// constants                                           
// general purpose registers                               
reg [4:0] t__reg__In_Raddr;
reg t__reg__In_Rclk;
reg [4:0] t__reg__In_Waddr;
reg t__reg__In_Wclk;
reg [7:0] t__reg__In_Wdata;
reg t__reg__In_Wen;
// wires                                               
wire [4:0] t__wire__In_Raddr;
wire t__wire__In_Rclk;
wire [4:0] t__wire__In_Waddr;
wire t__wire__In_Wclk;
wire [7:0] t__wire__In_Wdata;
wire t__wire__In_Wen;
wire [7:0] t__wire__Out_Rdata;

// assign statements (if any)                          
assign {t__wire__In_Raddr,t__wire__In_Rclk,t__wire__In_Waddr,t__wire__In_Wclk,t__wire__In_Wdata,t__wire__In_Wen} = {t__reg__In_Raddr,t__reg__In_Rclk,t__reg__In_Waddr,t__reg__In_Wclk,t__reg__In_Wdata,t__reg__In_Wen};
TOP tb (
// port map - connection between master ports and signals/registers   
	.In_Raddr(t__wire__In_Raddr),
	.In_Rclk(t__wire__In_Rclk),
	.In_Waddr(t__wire__In_Waddr),
	.In_Wclk(t__wire__In_Wclk),
	.In_Wdata(t__wire__In_Wdata),
	.In_Wen(t__wire__In_Wen),
	.Out_Rdata(t__wire__Out_Rdata)
);
initial 
begin 
#1000000 $stop;
end 
// In_Raddr[ 4 ]
initial
begin
	t__reg__In_Raddr[4] = 1'b0;
end 
// In_Raddr[ 3 ]
initial
begin
	t__reg__In_Raddr[3] = 1'b0;
end 
// In_Raddr[ 2 ]
initial
begin
	t__reg__In_Raddr[2] = 1'b0;
end 
// In_Raddr[ 1 ]
initial
begin
	t__reg__In_Raddr[1] = 1'b0;
	t__reg__In_Raddr[1] = #128500 1'b1;
	t__reg__In_Raddr[1] = #15500 1'b0;
end 
// In_Raddr[ 0 ]
initial
begin
	t__reg__In_Raddr[0] = 1'b0;
	t__reg__In_Raddr[0] = #128500 1'b1;
	t__reg__In_Raddr[0] = #15500 1'b0;
end 

// In_Rclk
initial
begin
	repeat(62)
	begin
		t__reg__In_Rclk = 1'b0;
		t__reg__In_Rclk = #8000 1'b1;
		# 8000;
	end
	t__reg__In_Rclk = 1'b0;
end 
// In_Waddr[ 4 ]
initial
begin
	t__reg__In_Waddr[4] = 1'b0;
end 
// In_Waddr[ 3 ]
initial
begin
	t__reg__In_Waddr[3] = 1'b0;
end 
// In_Waddr[ 2 ]
initial
begin
	t__reg__In_Waddr[2] = 1'b0;
	t__reg__In_Waddr[2] = #95500 1'b1;
	t__reg__In_Waddr[2] = #12500 1'b0;
end 
// In_Waddr[ 1 ]
initial
begin
	t__reg__In_Waddr[1] = 1'b0;
	t__reg__In_Waddr[1] = #71500 1'b1;
	t__reg__In_Waddr[1] = #24000 1'b0;
end 
// In_Waddr[ 0 ]
initial
begin
	t__reg__In_Waddr[0] = 1'b0;
	t__reg__In_Waddr[0] = #60000 1'b1;
	t__reg__In_Waddr[0] = #11500 1'b0;
	t__reg__In_Waddr[0] = #12500 1'b1;
	t__reg__In_Waddr[0] = #11500 1'b0;
end 

// In_Wclk
initial
begin
	repeat(83)
	begin
		t__reg__In_Wclk = 1'b0;
		t__reg__In_Wclk = #6000 1'b1;
		# 6000;
	end
	t__reg__In_Wclk = 1'b0;
end 
// In_Wdata[ 7 ]
initial
begin
	t__reg__In_Wdata[7] = 1'b0;
	t__reg__In_Wdata[7] = #60000 1'b1;
	t__reg__In_Wdata[7] = #48500 1'b0;
end 
// In_Wdata[ 6 ]
initial
begin
	t__reg__In_Wdata[6] = 1'b0;
	t__reg__In_Wdata[6] = #84000 1'b1;
	t__reg__In_Wdata[6] = #24500 1'b0;
end 
// In_Wdata[ 5 ]
initial
begin
	t__reg__In_Wdata[5] = 1'b0;
	t__reg__In_Wdata[5] = #60000 1'b1;
	t__reg__In_Wdata[5] = #24000 1'b0;
end 
// In_Wdata[ 4 ]
initial
begin
	t__reg__In_Wdata[4] = 1'b0;
	t__reg__In_Wdata[4] = #72000 1'b1;
	t__reg__In_Wdata[4] = #12000 1'b0;
	t__reg__In_Wdata[4] = #12000 1'b1;
	t__reg__In_Wdata[4] = #12500 1'b0;
end 
// In_Wdata[ 3 ]
initial
begin
	t__reg__In_Wdata[3] = 1'b0;
	t__reg__In_Wdata[3] = #60000 1'b1;
	t__reg__In_Wdata[3] = #48500 1'b0;
end 
// In_Wdata[ 2 ]
initial
begin
	t__reg__In_Wdata[2] = 1'b0;
	t__reg__In_Wdata[2] = #84000 1'b1;
	t__reg__In_Wdata[2] = #24500 1'b0;
end 
// In_Wdata[ 1 ]
initial
begin
	t__reg__In_Wdata[1] = 1'b0;
	t__reg__In_Wdata[1] = #60000 1'b1;
	t__reg__In_Wdata[1] = #24000 1'b0;
end 
// In_Wdata[ 0 ]
initial
begin
	t__reg__In_Wdata[0] = 1'b0;
	t__reg__In_Wdata[0] = #72000 1'b1;
	t__reg__In_Wdata[0] = #12000 1'b0;
	t__reg__In_Wdata[0] = #12000 1'b1;
	t__reg__In_Wdata[0] = #12500 1'b0;
end 

// In_Wen
initial
begin
	t__reg__In_Wen = 1'b0;
	t__reg__In_Wen = #60000 1'b1;
	t__reg__In_Wen = #48500 1'b0;
end 
initial 
begin 
#1000000 $stop;
end 
endmodule