dispselect.v

来自「基于verilog的交通灯设计」· Verilog 代码 · 共 19 行

module dispselect(CLK,D_OUT);

output [1:0] D_OUT;

input CLK;

reg [1:0] D_OUT;

always @(posedge CLK)
begin
	if(D_OUT < 2'b10)
		D_OUT <= D_OUT + 2'b01;
	else
		D_OUT <= 2'b01;
end
endmodule