up3_clock.map.summary

来自「在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Wed May 28 15:35:30 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : UP3_CLOCK
Top-level Entity Name : UP3_CLOCK
Family : Cyclone
Total logic elements : 441
Total pins : 21
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0