up3_clock.map.qmsg

在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 28 15:35:22 2008 " "Info: Processing started: Wed May 28 15:35:22 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UP3_CLOCK -c UP3_CLOCK " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UP3_CLOCK -c UP3_CLOCK" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UP3_CLOCK.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file UP3_CLOCK.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UP3_CLOCK-a " "Info: Found design unit 1: UP3_CLOCK-a" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 UP3_CLOCK " "Info: Found entity 1: UP3_CLOCK" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UP3_CLOCK " "Info: Elaborating entity \"UP3_CLOCK\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DipSwitch1 UP3_CLOCK.vhd(483) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(483): signal \"DipSwitch1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 483 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TEMP_BCD_SECD0 UP3_CLOCK.vhd(531) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(531): signal \"TEMP_BCD_SECD0\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 531 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "TEMP_BCD_SECD1 UP3_CLOCK.vhd(532) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(532): signal \"TEMP_BCD_SECD1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 532 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}