up3_clock.tan.qmsg

在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒

{ "Info" "ITDB_TSU_RESULT" "TEMP_BCD_HRD1\[3\] DipSwitch2 CLK_48MHZ 10.432 ns register " "Info: tsu for register \"TEMP_BCD_HRD1\[3\]\" (data pin = \"DipSwitch2\", clock pin = \"CLK_48MHZ\") is 10.432 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.337 ns + Longest pin register " "Info: + Longest pin to register delay is 13.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DipSwitch2 1 PIN PIN_59 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_59; Fanout = 10; PIN Node = 'DipSwitch2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DipSwitch2 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.967 ns) + CELL(0.590 ns) 10.026 ns TEMP_BCD_HRD0\[3\]~400 2 COMB LC_X26_Y2_N6 1 " "Info: 2: + IC(7.967 ns) + CELL(0.590 ns) = 10.026 ns; Loc. = LC_X26_Y2_N6; Fanout = 1; COMB Node = 'TEMP_BCD_HRD0\[3\]~400'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.557 ns" { DipSwitch2 TEMP_BCD_HRD0[3]~400 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 542 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.991 ns) + CELL(0.114 ns) 12.131 ns TEMP_BCD_HRD1\[3\]~380 3 COMB LC_X23_Y10_N0 4 " "Info: 3: + IC(1.991 ns) + CELL(0.114 ns) = 12.131 ns; Loc. = LC_X23_Y10_N0; Fanout = 4; COMB Node = 'TEMP_BCD_HRD1\[3\]~380'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.105 ns" { TEMP_BCD_HRD0[3]~400 TEMP_BCD_HRD1[3]~380 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 542 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.728 ns) + CELL(0.478 ns) 13.337 ns TEMP_BCD_HRD1\[3\] 4 REG LC_X24_Y10_N6 3 " "Info: 4: + IC(0.728 ns) + CELL(0.478 ns) = 13.337 ns; Loc. = LC_X24_Y10_N6; Fanout = 3; REG Node = 'TEMP_BCD_HRD1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.206 ns" { TEMP_BCD_HRD1[3]~380 TEMP_BCD_HRD1[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 542 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.651 ns ( 19.88 % ) " "Info: Total cell delay = 2.651 ns ( 19.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.686 ns ( 80.12 % ) " "Info: Total interconnect delay = 10.686 ns ( 80.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.337 ns" { DipSwitch2 TEMP_BCD_HRD0[3]~400 TEMP_BCD_HRD1[3]~380 TEMP_BCD_HRD1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.337 ns" { DipSwitch2 DipSwitch2~out0 TEMP_BCD_HRD0[3]~400 TEMP_BCD_HRD1[3]~380 TEMP_BCD_HRD1[3] } { 0.000ns 0.000ns 7.967ns 1.991ns 0.728ns } { 0.000ns 1.469ns 0.590ns 0.114ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 542 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_48MHZ\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 112 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 112; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns TEMP_BCD_HRD1\[3\] 2 REG LC_X24_Y10_N6 3 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X24_Y10_N6; Fanout = 3; REG Node = 'TEMP_BCD_HRD1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { CLK_48MHZ TEMP_BCD_HRD1[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 542 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { CLK_48MHZ TEMP_BCD_HRD1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { CLK_48MHZ CLK_48MHZ~out0 TEMP_BCD_HRD1[3] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.337 ns" { DipSwitch2 TEMP_BCD_HRD0[3]~400 TEMP_BCD_HRD1[3]~380 TEMP_BCD_HRD1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.337 ns" { DipSwitch2 DipSwitch2~out0 TEMP_BCD_HRD0[3]~400 TEMP_BCD_HRD1[3]~380 TEMP_BCD_HRD1[3] } { 0.000ns 0.000ns 7.967ns 1.991ns 0.728ns } { 0.000ns 1.469ns 0.590ns 0.114ns 0.478ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { CLK_48MHZ TEMP_BCD_HRD1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { CLK_48MHZ CLK_48MHZ~out0 TEMP_BCD_HRD1[3] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK_48MHZ ALARM_LED BCD_HRD0\[0\] 25.063 ns register " "Info: tco from clock \"CLK_48MHZ\" to destination pin \"ALARM_LED\" through register \"BCD_HRD0\[0\]\" is 25.063 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ source 12.153 ns + Longest register " "Info: + Longest clock path from clock \"CLK_48MHZ\" to source register is 12.153 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 112 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 112; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_400HZ 2 REG LC_X8_Y10_N9 109 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 109; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK_48MHZ CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.935 ns) 7.593 ns CLK_10HZ 3 REG LC_X9_Y10_N2 27 " "Info: 3: + IC(3.509 ns) + CELL(0.935 ns) = 7.593 ns; Loc. = LC_X9_Y10_N2; Fanout = 27; REG Node = 'CLK_10HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.444 ns" { CLK_400HZ CLK_10HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.849 ns) + CELL(0.711 ns) 12.153 ns BCD_HRD0\[0\] 4 REG LC_X28_Y9_N5 7 " "Info: 4: + IC(3.849 ns) + CELL(0.711 ns) = 12.153 ns; Loc. = LC_X28_Y9_N5; Fanout = 7; REG Node = 'BCD_HRD0\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.560 ns" { CLK_10HZ BCD_HRD0[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.33 % ) " "Info: Total cell delay = 4.050 ns ( 33.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.103 ns ( 66.67 % ) " "Info: Total interconnect delay = 8.103 ns ( 66.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.153 ns" { CLK_48MHZ CLK_400HZ CLK_10HZ BCD_HRD0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.153 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ CLK_10HZ BCD_HRD0[0] } { 0.000ns 0.000ns 0.745ns 3.509ns 3.849ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.686 ns + Longest register pin " "Info: + Longest register to pin delay is 12.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BCD_HRD0\[0\] 1 REG LC_X28_Y9_N5 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y9_N5; Fanout = 7; REG Node = 'BCD_HRD0\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BCD_HRD0[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.611 ns) + CELL(0.590 ns) 2.201 ns ALARM_LED~242 2 COMB LC_X24_Y11_N9 1 " "Info: 2: + IC(1.611 ns) + CELL(0.590 ns) = 2.201 ns; Loc. = LC_X24_Y11_N9; Fanout = 1; COMB Node = 'ALARM_LED~242'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.201 ns" { BCD_HRD0[0] ALARM_LED~242 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.590 ns) 4.318 ns ALARM_LED~244 3 COMB LC_X26_Y8_N6 1 " "Info: 3: + IC(1.527 ns) + CELL(0.590 ns) = 4.318 ns; Loc. = LC_X26_Y8_N6; Fanout = 1; COMB Node = 'ALARM_LED~244'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.117 ns" { ALARM_LED~242 ALARM_LED~244 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.507 ns) + CELL(0.442 ns) 6.267 ns ALARM_LED~248 4 COMB LC_X24_Y9_N4 1 " "Info: 4: + IC(1.507 ns) + CELL(0.442 ns) = 6.267 ns; Loc. = LC_X24_Y9_N4; Fanout = 1; COMB Node = 'ALARM_LED~248'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.949 ns" { ALARM_LED~244 ALARM_LED~248 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.295 ns) + CELL(2.124 ns) 12.686 ns ALARM_LED 5 PIN PIN_55 0 " "Info: 5: + IC(4.295 ns) + CELL(2.124 ns) = 12.686 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'ALARM_LED'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.419 ns" { ALARM_LED~248 ALARM_LED } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 29.53 % ) " "Info: Total cell delay = 3.746 ns ( 29.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.940 ns ( 70.47 % ) " "Info: Total interconnect delay = 8.940 ns ( 70.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.686 ns" { BCD_HRD0[0] ALARM_LED~242 ALARM_LED~244 ALARM_LED~248 ALARM_LED } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.686 ns" { BCD_HRD0[0] ALARM_LED~242 ALARM_LED~244 ALARM_LED~248 ALARM_LED } { 0.000ns 1.611ns 1.527ns 1.507ns 4.295ns } { 0.000ns 0.590ns 0.590ns 0.442ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.153 ns" { CLK_48MHZ CLK_400HZ CLK_10HZ BCD_HRD0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.153 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ CLK_10HZ BCD_HRD0[0] } { 0.000ns 0.000ns 0.745ns 3.509ns 3.849ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.686 ns" { BCD_HRD0[0] ALARM_LED~242 ALARM_LED~244 ALARM_LED~248 ALARM_LED } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.686 ns" { BCD_HRD0[0] ALARM_LED~242 ALARM_LED~244 ALARM_LED~248 ALARM_LED } { 0.000ns 1.611ns 1.527ns 1.507ns 4.295ns } { 0.000ns 0.590ns 0.590ns 0.442ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset RESET_LED 11.165 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"RESET_LED\" is 11.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_23 192 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 192; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.572 ns) + CELL(2.124 ns) 11.165 ns RESET_LED 2 PIN PIN_53 0 " "Info: 2: + IC(7.572 ns) + CELL(2.124 ns) = 11.165 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'RESET_LED'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.696 ns" { reset RESET_LED } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.593 ns ( 32.18 % ) " "Info: Total cell delay = 3.593 ns ( 32.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.572 ns ( 67.82 % ) " "Info: Total interconnect delay = 7.572 ns ( 67.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.165 ns" { reset RESET_LED } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.165 ns" { reset reset~out0 RESET_LED } { 0.000ns 0.000ns 7.572ns } { 0.000ns 1.469ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "BCD_TSEC\[1\] DipSwitch1 CLK_48MHZ 1.838 ns register " "Info: th for register \"BCD_TSEC\[1\]\" (data pin = \"DipSwitch1\", clock pin = \"CLK_48MHZ\") is 1.838 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ destination 12.152 ns + Longest register " "Info: + Longest clock path from clock \"CLK_48MHZ\" to destination register is 12.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 112 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 112; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_400HZ 2 REG LC_X8_Y10_N9 109 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 109; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK_48MHZ CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.935 ns) 7.593 ns CLK_10HZ 3 REG LC_X9_Y10_N2 27 " "Info: 3: + IC(3.509 ns) + CELL(0.935 ns) = 7.593 ns; Loc. = LC_X9_Y10_N2; Fanout = 27; REG Node = 'CLK_10HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.444 ns" { CLK_400HZ CLK_10HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.848 ns) + CELL(0.711 ns) 12.152 ns BCD_TSEC\[1\] 4 REG LC_X27_Y7_N9 6 " "Info: 4: + IC(3.848 ns) + CELL(0.711 ns) = 12.152 ns; Loc. = LC_X27_Y7_N9; Fanout = 6; REG Node = 'BCD_TSEC\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.559 ns" { CLK_10HZ BCD_TSEC[1] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.33 % ) " "Info: Total cell delay = 4.050 ns ( 33.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.102 ns ( 66.67 % ) " "Info: Total interconnect delay = 8.102 ns ( 66.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.152 ns" { CLK_48MHZ CLK_400HZ CLK_10HZ BCD_TSEC[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.152 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ CLK_10HZ BCD_TSEC[1] } { 0.000ns 0.000ns 0.745ns 3.509ns 3.848ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.329 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns DipSwitch1 1 PIN PIN_58 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_58; Fanout = 5; PIN Node = 'DipSwitch1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DipSwitch1 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.993 ns) + CELL(0.867 ns) 10.329 ns BCD_TSEC\[1\] 2 REG LC_X27_Y7_N9 6 " "Info: 2: + IC(7.993 ns) + CELL(0.867 ns) = 10.329 ns; Loc. = LC_X27_Y7_N9; Fanout = 6; REG Node = 'BCD_TSEC\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.860 ns" { DipSwitch1 BCD_TSEC[1] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 22.62 % ) " "Info: Total cell delay = 2.336 ns ( 22.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.993 ns ( 77.38 % ) " "Info: Total interconnect delay = 7.993 ns ( 77.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.329 ns" { DipSwitch1 BCD_TSEC[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.329 ns" { DipSwitch1 DipSwitch1~out0 BCD_TSEC[1] } { 0.000ns 0.000ns 7.993ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.152 ns" { CLK_48MHZ CLK_400HZ CLK_10HZ BCD_TSEC[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.152 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ CLK_10HZ BCD_TSEC[1] } { 0.000ns 0.000ns 0.745ns 3.509ns 3.848ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.329 ns" { DipSwitch1 BCD_TSEC[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.329 ns" { DipSwitch1 DipSwitch1~out0 BCD_TSEC[1] } { 0.000ns 0.000ns 7.993ns } { 0.000ns 1.469ns 0.867ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}