up3_clock.tan.qmsg

来自「在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒」· QMSG 代码 · 共 14 行 · 第 1/4 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_10HZ " "Info: Detected ripple clock \"CLK_10HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_10HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_400HZ " "Info: Detected ripple clock \"CLK_400HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_400HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_48MHZ register BCD_SECD1\[0\] register DATA_BUS_VALUE\[0\] 120.39 MHz 8.306 ns Internal " "Info: Clock \"CLK_48MHZ\" has Internal fmax of 120.39 MHz between source register \"BCD_SECD1\[0\]\" and destination register \"DATA_BUS_VALUE\[0\]\" (period= 8.306 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.252 ns + Longest register register " "Info: + Longest register to register delay is 3.252 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BCD_SECD1\[0\] 1 REG LC_X26_Y6_N2 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y6_N2; Fanout = 6; REG Node = 'BCD_SECD1\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { BCD_SECD1[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.614 ns) + CELL(0.114 ns) 1.728 ns Selector9~225 2 COMB LC_X28_Y9_N0 1 " "Info: 2: + IC(1.614 ns) + CELL(0.114 ns) = 1.728 ns; Loc. = LC_X28_Y9_N0; Fanout = 1; COMB Node = 'Selector9~225'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.728 ns" { BCD_SECD1[0] Selector9~225 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.741 ns) + CELL(0.292 ns) 2.761 ns Selector9~229 3 COMB LC_X27_Y9_N7 1 " "Info: 3: + IC(0.741 ns) + CELL(0.292 ns) = 2.761 ns; Loc. = LC_X27_Y9_N7; Fanout = 1; COMB Node = 'Selector9~229'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.033 ns" { Selector9~225 Selector9~229 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 3.252 ns DATA_BUS_VALUE\[0\] 4 REG LC_X27_Y9_N8 2 " "Info: 4: + IC(0.182 ns) + CELL(0.309 ns) = 3.252 ns; Loc. = LC_X27_Y9_N8; Fanout = 2; REG Node = 'DATA_BUS_VALUE\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.491 ns" { Selector9~229 DATA_BUS_VALUE[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.715 ns ( 21.99 % ) " "Info: Total cell delay = 0.715 ns ( 21.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.537 ns ( 78.01 % ) " "Info: Total interconnect delay = 2.537 ns ( 78.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.252 ns" { BCD_SECD1[0] Selector9~225 Selector9~229 DATA_BUS_VALUE[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.252 ns" { BCD_SECD1[0] Selector9~225 Selector9~229 DATA_BUS_VALUE[0] } { 0.000ns 1.614ns 0.741ns 0.182ns } { 0.000ns 0.114ns 0.292ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.793 ns - Smallest " "Info: - Smallest clock skew is -4.793 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ destination 7.357 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_48MHZ\" to destination register is 7.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 112 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 112; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_400HZ 2 REG LC_X8_Y10_N9 109 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 109; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK_48MHZ CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(0.711 ns) 7.357 ns DATA_BUS_VALUE\[0\] 3 REG LC_X27_Y9_N8 2 " "Info: 3: + IC(3.497 ns) + CELL(0.711 ns) = 7.357 ns; Loc. = LC_X27_Y9_N8; Fanout = 2; REG Node = 'DATA_BUS_VALUE\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { CLK_400HZ DATA_BUS_VALUE[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.34 % ) " "Info: Total cell delay = 3.115 ns ( 42.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.242 ns ( 57.66 % ) " "Info: Total interconnect delay = 4.242 ns ( 57.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.357 ns" { CLK_48MHZ CLK_400HZ DATA_BUS_VALUE[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.357 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ DATA_BUS_VALUE[0] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ source 12.150 ns - Longest register " "Info: - Longest clock path from clock \"CLK_48MHZ\" to source register is 12.150 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 112 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 112; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_400HZ 2 REG LC_X8_Y10_N9 109 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 109; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK_48MHZ CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.509 ns) + CELL(0.935 ns) 7.593 ns CLK_10HZ 3 REG LC_X9_Y10_N2 27 " "Info: 3: + IC(3.509 ns) + CELL(0.935 ns) = 7.593 ns; Loc. = LC_X9_Y10_N2; Fanout = 27; REG Node = 'CLK_10HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.444 ns" { CLK_400HZ CLK_10HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.846 ns) + CELL(0.711 ns) 12.150 ns BCD_SECD1\[0\] 4 REG LC_X26_Y6_N2 6 " "Info: 4: + IC(3.846 ns) + CELL(0.711 ns) = 12.150 ns; Loc. = LC_X26_Y6_N2; Fanout = 6; REG Node = 'BCD_SECD1\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.557 ns" { CLK_10HZ BCD_SECD1[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.33 % ) " "Info: Total cell delay = 4.050 ns ( 33.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.100 ns ( 66.67 % ) " "Info: Total interconnect delay = 8.100 ns ( 66.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.150 ns" { CLK_48MHZ CLK_400HZ CLK_10HZ BCD_SECD1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.150 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ CLK_10HZ BCD_SECD1[0] } { 0.000ns 0.000ns 0.745ns 3.509ns 3.846ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.357 ns" { CLK_48MHZ CLK_400HZ DATA_BUS_VALUE[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.357 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ DATA_BUS_VALUE[0] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.150 ns" { CLK_48MHZ CLK_400HZ CLK_10HZ BCD_SECD1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.150 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ CLK_10HZ BCD_SECD1[0] } { 0.000ns 0.000ns 0.745ns 3.509ns 3.846ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 484 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.252 ns" { BCD_SECD1[0] Selector9~225 Selector9~229 DATA_BUS_VALUE[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.252 ns" { BCD_SECD1[0] Selector9~225 Selector9~229 DATA_BUS_VALUE[0] } { 0.000ns 1.614ns 0.741ns 0.182ns } { 0.000ns 0.114ns 0.292ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.357 ns" { CLK_48MHZ CLK_400HZ DATA_BUS_VALUE[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.357 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ DATA_BUS_VALUE[0] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.150 ns" { CLK_48MHZ CLK_400HZ CLK_10HZ BCD_SECD1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "12.150 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ CLK_10HZ BCD_SECD1[0] } { 0.000ns 0.000ns 0.745ns 3.509ns 3.846ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK_48MHZ 9 " "Warning: Circuit may not operate. Detected 9 non-operational path(s) clocked by clock \"CLK_48MHZ\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ALARM_BCD_HRD1\[3\] DATA_BUS_VALUE\[3\] CLK_48MHZ 1.867 ns " "Info: Found hold time violation between source  pin or register \"ALARM_BCD_HRD1\[3\]\" and destination pin or register \"DATA_BUS_VALUE\[3\]\" for clock \"CLK_48MHZ\" (Hold time is 1.867 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.448 ns + Largest " "Info: + Largest clock skew is 4.448 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ destination 7.357 ns + Longest register " "Info: + Longest clock path from clock \"CLK_48MHZ\" to destination register is 7.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 112 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 112; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_400HZ 2 REG LC_X8_Y10_N9 109 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 109; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.680 ns" { CLK_48MHZ CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(0.711 ns) 7.357 ns DATA_BUS_VALUE\[3\] 3 REG LC_X25_Y9_N9 2 " "Info: 3: + IC(3.497 ns) + CELL(0.711 ns) = 7.357 ns; Loc. = LC_X25_Y9_N9; Fanout = 2; REG Node = 'DATA_BUS_VALUE\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { CLK_400HZ DATA_BUS_VALUE[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.34 % ) " "Info: Total cell delay = 3.115 ns ( 42.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.242 ns ( 57.66 % ) " "Info: Total interconnect delay = 4.242 ns ( 57.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.357 ns" { CLK_48MHZ CLK_400HZ DATA_BUS_VALUE[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.357 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ DATA_BUS_VALUE[3] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_48MHZ source 2.909 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_48MHZ\" to source register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK_48MHZ 1 CLK PIN_29 112 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 112; CLK Node = 'CLK_48MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK_48MHZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns ALARM_BCD_HRD1\[3\] 2 REG LC_X26_Y9_N8 4 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X26_Y9_N8; Fanout = 4; REG Node = 'ALARM_BCD_HRD1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { CLK_48MHZ ALARM_BCD_HRD1[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 542 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_48MHZ ALARM_BCD_HRD1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_48MHZ CLK_48MHZ~out0 ALARM_BCD_HRD1[3] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.357 ns" { CLK_48MHZ CLK_400HZ DATA_BUS_VALUE[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.357 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ DATA_BUS_VALUE[3] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_48MHZ ALARM_BCD_HRD1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_48MHZ CLK_48MHZ~out0 ALARM_BCD_HRD1[3] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 542 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.372 ns - Shortest register register " "Info: - Shortest register to register delay is 2.372 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ALARM_BCD_HRD1\[3\] 1 REG LC_X26_Y9_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N8; Fanout = 4; REG Node = 'ALARM_BCD_HRD1\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ALARM_BCD_HRD1[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 542 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.554 ns) + CELL(0.292 ns) 0.846 ns Selector6~221 2 COMB LC_X26_Y9_N0 1 " "Info: 2: + IC(0.554 ns) + CELL(0.292 ns) = 0.846 ns; Loc. = LC_X26_Y9_N0; Fanout = 1; COMB Node = 'Selector6~221'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.846 ns" { ALARM_BCD_HRD1[3] Selector6~221 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.743 ns) + CELL(0.292 ns) 1.881 ns Selector6~222 3 COMB LC_X25_Y9_N8 1 " "Info: 3: + IC(0.743 ns) + CELL(0.292 ns) = 1.881 ns; Loc. = LC_X25_Y9_N8; Fanout = 1; COMB Node = 'Selector6~222'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.035 ns" { Selector6~221 Selector6~222 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 2.372 ns DATA_BUS_VALUE\[3\] 4 REG LC_X25_Y9_N9 2 " "Info: 4: + IC(0.182 ns) + CELL(0.309 ns) = 2.372 ns; Loc. = LC_X25_Y9_N9; Fanout = 2; REG Node = 'DATA_BUS_VALUE\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.491 ns" { Selector6~222 DATA_BUS_VALUE[3] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.893 ns ( 37.65 % ) " "Info: Total cell delay = 0.893 ns ( 37.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.479 ns ( 62.35 % ) " "Info: Total interconnect delay = 1.479 ns ( 62.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.372 ns" { ALARM_BCD_HRD1[3] Selector6~221 Selector6~222 DATA_BUS_VALUE[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.372 ns" { ALARM_BCD_HRD1[3] Selector6~221 Selector6~222 DATA_BUS_VALUE[3] } { 0.000ns 0.554ns 0.743ns 0.182ns } { 0.000ns 0.292ns 0.292ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/实验5-时钟设计-1/UP3_CLOCK.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.357 ns" { CLK_48MHZ CLK_400HZ DATA_BUS_VALUE[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.357 ns" { CLK_48MHZ CLK_48MHZ~out0 CLK_400HZ DATA_BUS_VALUE[3] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { CLK_48MHZ ALARM_BCD_HRD1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { CLK_48MHZ CLK_48MHZ~out0 ALARM_BCD_HRD1[3] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.372 ns" { ALARM_BCD_HRD1[3] Selector6~221 Selector6~222 DATA_BUS_VALUE[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.372 ns" { ALARM_BCD_HRD1[3] Selector6~221 Selector6~222 DATA_BUS_VALUE[3] } { 0.000ns 0.554ns 0.743ns 0.182ns } { 0.000ns 0.292ns 0.292ns 0.309ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}